On Mon, Oct 27, 2014 at 2:38 PM, Andrew Bresticker
<abrestic@xxxxxxxxxxxx> wrote:
> No byte swapping is necessary for accessing the GIC registers.
>
> Signed-off-by: Andrew Bresticker <abrestic@xxxxxxxxxxxx>
> ---
> drivers/irqchip/irq-mips-gic.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
> index 61ac482..7ec3c18 100644
> --- a/drivers/irqchip/irq-mips-gic.c
> +++ b/drivers/irqchip/irq-mips-gic.c
> @@ -37,12 +37,12 @@ static void __gic_irq_dispatch(void);
>
> static inline unsigned int gic_read(unsigned int reg)
> {
> - return readl(gic_base + reg);
> + return __raw_readl(gic_base + reg);
> }
>
> static inline void gic_write(unsigned int reg, unsigned int val)
> {
> - writel(val, gic_base + reg);
> + __raw_writel(val, gic_base + reg);
> }
Hi Andrew,
I just ran into a related problem on bcm3384, a big-endian platform on
which readl/writel perform extra endian swaps (CONFIG_SWAP_IO_SPACE).
My solution was twofold:
- Change the irq_reg_{readl,writel} macros so that they can be
configured to use the __raw_ variants on individual platforms
- Use irq_reg_{readl,writel} instead of directly invoking
__raw_{readl,writel} in our irqchip driver, so that the irqchip driver
code always uses the same I/O accessors as the helper functions we're
using from kernel/irq/generic-chip.c
The two commits are posted here:
https://github.com/cernekee/linux/commit/52923b7bbaf99385a813a6f54de6ff810e11638c
https://github.com/cernekee/linux/commit/371f990bd1b9e980ffbea63f6375d13156f3e731
I haven't submitted them yet since they need to be retested on our LE platforms.
Do you think a similar approach might be suitable for the irq-mips-gic driver?
