[PATCH 1/3] MIPS: Malta: Use __raw_{readl,writel} to access MSC registers

[Andrew Bresticker <abrestic@xxxxxxxxxxxx>]

No byte swapping is necessary for accesses to the MSC registers.

Signed-off-by: Andrew Bresticker <abrestic@xxxxxxxxxxxx>
---
 arch/mips/mti-malta/malta-int.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index 6ea4033..d1392f8 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -295,9 +295,10 @@ void __init arch_init_irq(void)
 		if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) {
 			_msc01_biu_base = ioremap_nocache(MSC01_BIU_REG_BASE,
 						MSC01_BIU_ADDRSPACE_SZ);
-			gic_present = (readl(_msc01_biu_base + MSC01_SC_CFG_OFS) &
-					MSC01_SC_CFG_GICPRES_MSK) >>
-					MSC01_SC_CFG_GICPRES_SHF;
+			gic_present =
+			  (__raw_readl(_msc01_biu_base + MSC01_SC_CFG_OFS) &
+			   MSC01_SC_CFG_GICPRES_MSK) >>
+			  MSC01_SC_CFG_GICPRES_SHF;
 		}
 	}
 	if (gic_present)
@@ -335,8 +336,8 @@ void __init arch_init_irq(void)
 			 MIPS_GIC_IRQ_BASE);
 		if (!mips_cm_present()) {
 			/* Enable the GIC */
-			i = readl(_msc01_biu_base + MSC01_SC_CFG_OFS);
-			writel(i | (0x1 << MSC01_SC_CFG_GICENA_SHF),
+			i = __raw_readl(_msc01_biu_base + MSC01_SC_CFG_OFS);
+			__raw_writel(i | (0x1 << MSC01_SC_CFG_GICENA_SHF),
 				 _msc01_biu_base + MSC01_SC_CFG_OFS);
 			pr_debug("GIC Enabled\n");
 		}
-- 
2.1.0.rc2.206.gedb03e5