On Tue, Oct 07, 2014 at 09:13:22AM +0000, Matthew Fortune wrote: > From what I can see the out-of-line execution of delay slot instructions > will break micromips R3 addiupc, and all MIPS32r6 and MIPS64r6 PC-relative > instructions (inc load/store) as they will have the wrong base. Is there > anything in the current set of proposals that can address this (beyond > adding restrictions to what is ABI allowed in FPU branch delay slots)? Yes. If a trampoline is being generated to replace the delay slot instruction, it can just contain more complex code to duplicate what the PC-relative instruction would have done. Since the ABI already assumes a stack is available, it can use the stack to backup registers it needs for scratch space and restore them. > This is an issue whether the stack is executable or not but does directly > relate to the topic of FPU emulation. It sounds like the kernel would not > be able to emulate a pc-relative load/store even if it was a special case > as it would not run in the correct MM context? [be gentle, I'm no expert > in this area]. Really everything should be done in the kernel, and it's not as hard as people are making it look. The kernel _already_ has to enforce MM context permissions for every syscall that reads or writes user memory (e.g. futex with PI mutexes or FUTEX_WAKE_OP, or even simple things like read/write) so there's no reason it can't do emulated loads/stores the exact same way. Rich
