On Thu, 24 Jul 2014 04:38:01 +0400 Max Filippov <jcmvbkbc@xxxxxxxxx> wrote: > On Thu, Jul 24, 2014 at 1:17 AM, Andrew Morton > <akpm@xxxxxxxxxxxxxxxxxxxx> wrote: > > Fifthly, it would be very useful to publish the performance testing > > results for at least one architecture so that we can determine the > > patchset's desirability. And perhaps to motivate other architectures > > to implement this. > > What sort of performance numbers would be relevant? > For xtensa this patch enables highmem use for cores with aliasing cache, > that is access to a gigabyte of memory (typical on KC705 FPGA board) vs. > only 128MBytes of low memory, which is highly desirable. But performance > comparison of these two configurations seems to make little sense. > OTOH performance comparison of highmem variants with and without > cache aliasing would show the quality of our cache flushing code. I'd assumed the patch was making cache coloring available as a performance tweak. But you appear to be saying that the (high) memory is simply unavailable for such cores without this change. I think. Please ensure that v3's changelog explains the full reason for the patch. Assume you're talking to all-the-worlds-an-x86 dummies, OK?
