Hi Andrew, thanks for your feedback, I'll address your points in the next version of this series. On Thu, Jul 24, 2014 at 1:17 AM, Andrew Morton <akpm@xxxxxxxxxxxxxxxxxxxx> wrote: > Fifthly, it would be very useful to publish the performance testing > results for at least one architecture so that we can determine the > patchset's desirability. And perhaps to motivate other architectures > to implement this. What sort of performance numbers would be relevant? For xtensa this patch enables highmem use for cores with aliasing cache, that is access to a gigabyte of memory (typical on KC705 FPGA board) vs. only 128MBytes of low memory, which is highly desirable. But performance comparison of these two configurations seems to make little sense. OTOH performance comparison of highmem variants with and without cache aliasing would show the quality of our cache flushing code. -- Thanks. -- Max
