Hi Sergei,
On 07/15/2014 05:09 PM, Sergei Shtylyov wrote:
> Hello.
>
> On 07/15/2014 05:09 PM, Markos Chandras wrote:
>
>> From: Leonid Yegoshin <Leonid.Yegoshin@xxxxxxxxxx>
>
>> MIPSr5 added support for unique exception codes for the Read-Inhibit
>> and Execute-Inhibit exceptions.
>
>> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@xxxxxxxxxx>
>> Signed-off-by: Markos Chandras <markos.chandras@xxxxxxxxxx>
> [...]
>
>> diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
>> index 8219c0a5f77e..be13f2879c84 100644
>> --- a/arch/mips/include/asm/cpu.h
>> +++ b/arch/mips/include/asm/cpu.h
>> @@ -364,6 +364,7 @@ enum cpu_type_enum {
>> #define MIPS_CPU_SEGMENTS 0x04000000ull /* CPU supports
>> Segmentation Control registers */
>> #define MIPS_CPU_EVA 0x80000000ull /* CPU supports Enhanced
>> Virtual Addressing */
>> #define MIPS_CPU_HTW 0x100000000ull /* CPU support Hardware
>> Page Table Walker */
>> +#define MIPS_CPU_RIXIEX 0x200000000ull /* CPU has unique
>> exception codes for {Read, Execute}-Inhibit exceptions */
>
> I think this conflicts with the MAAR patchset.
>
> WBR, Sergei
>
Well yes, but it's easy to resolve these conflicts.
--
markos
