Hi David, On 07/15/2014 07:50 PM, David Daney wrote: > On 07/15/2014 06:09 AM, Markos Chandras wrote: >> Hi, >> >> This patchset adds support for unique RI/XI exceptions. This feature has >> been added in MIPSr5. Using this feature, we reduce the time it takes >> to deal with a TLB exception caused by the RI/XI bits since the TLB load >> handler is skipped and we use the tlb_do_page_failt_0 path directly. >> >> This patch depends on the Hardware Page Table Walker (HTW) patchset >> http://www.linux-mips.org/archives/linux-mips/2014-07/msg00195.html > > They are unrelated features, why the dependency? Because of the conflicts in cpu.h and cpu-features.h. I am just trying to make Ralf' life easier when he tries to determine the order to apply this patches. -- markos
