Now what should I do? Change MAX_PHYSMEM_BITS and XPHYSADDR to 49 bits in a separte patch? Huacai On Thu, Jun 5, 2014 at 1:22 AM, David Daney <ddaney.cavm@xxxxxxxxx> wrote: > On 06/03/2014 11:46 PM, Ralf Baechle wrote: >> >> >> A more important value which I haven't noticed the Looongson patches to >> modify is SECTION_SIZE_BITS in <asm/sparsemem.h>: >> >> #if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) && >> defined(CONFIG_PAGE_SIZE_64KB) >> # define SECTION_SIZE_BITS 29 >> #else >> # define SECTION_SIZE_BITS 28 >> #endif >> >> Don't ask me why its definition depends on MIPS_HUGE_TLB_SUPPORT and >> PAGE_SIZE_64KB - the value describes the larges chunk of contiguous >> memory (that is for example memory per node) and that doesn't depend >> on these CONFIG_* symbols. >> > > I think I can answer that. We do the same thing for OCTEON I think. > > IIRC, with SPARSEMEM, you cannot allocate high order pages that span > multiple sections. Therefore you have to have the sections be at least as > large as a huge page. in the case of CONFIG_PAGE_SIZE_64KB, the huge pages > are 512MB which doesn't fit in 28 bits. > > David. > > >> Ralf >> >> > >
