On 06/03/2014 03:47 PM, Ralf Baechle wrote:
[...]
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -51,8 +51,14 @@
* Returns the physical address of a CKSEGx / XKPHYS address
*/
#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
+
+#ifndef CONFIG_NUMA
#define XPHYSADDR(a) ((_ACAST64_(a)) & \
_CONST64_(0x000000ffffffffff))
+#else
+#define XPHYSADDR(a) ((_ACAST64_(a)) & \
+ _CONST64_(0x0000ffffffffffff))
+#endif
The mask in XPHYSADDR is a function of the processor architecture, not
imlementation, not NUMA. The latest version of the MIPS architecture
permits PABITS to be as large as 49 bits, so the mask should be
0x0001ffffffffffff. Always.
diff --git a/arch/mips/include/asm/sparsemem.h b/arch/mips/include/asm/sparsemem.h
index d2da53c..c001a90 100644
--- a/arch/mips/include/asm/sparsemem.h
+++ b/arch/mips/include/asm/sparsemem.h
@@ -11,7 +11,12 @@
#else
# define SECTION_SIZE_BITS 28
#endif
+
+#ifdef CONFIG_NUMA
+#define MAX_PHYSMEM_BITS 48
+#else
#define MAX_PHYSMEM_BITS 35
+#endif
Essentially the same comment as for XPHYSADDR above.
Are you saying to change it to 49 unconditionally for all configurations?
That would work for OCTEON too, where we have had to increase it to 42.
What are the implications for kernel data structures if this is set many
orders of magnitude greater than the actual number of bits used on a system?
Ralf
