In cores which implement the MT ASE, the CPUNum in the EBase register is
a concatenation of the core number & the VPE ID within that core. In
order to retrieve the correct core number CPUNum must be shifted
appropriately to remove the VPE ID bits.
Signed-off-by: Paul Burton <paul.burton@xxxxxxxxxx>
---
arch/mips/kernel/cpu-probe.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 34df5af..79526b2 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -421,8 +421,11 @@ static void decode_configs(struct cpuinfo_mips *c)
mips_probe_watch_registers(c);
#ifndef CONFIG_MIPS_CPS
- if (cpu_has_mips_r2)
+ if (cpu_has_mips_r2) {
c->core = read_c0_ebase() & 0x3ff;
+ if (cpu_has_mipsmt)
+ c->core >>= fls(smp_num_siblings) - 1;
+ }
#endif
}
--
1.8.5.3
