Changing MSAEn on the MIPS P5600 core creates an execution hazard which
must be cleared before any subsequent MSA instructions are executed.
This is similar to the FPU with which MSA is linked. Since all cores
with MSA support are >MIPSR2 the {en,dis}able_fpu_hazard macros will
always expand to the ehb instruction required, so they are simply
re-used.
Reported-by: James Hogan <james.hogan@xxxxxxxxxx>
Reviewed-by: James Hogan <james.hogan@xxxxxxxxxx>
Tested-by: James Hogan <james.hogan@xxxxxxxxxx>
Signed-off-by: Paul Burton <paul.burton@xxxxxxxxxx>
---
This patch would ideally be applied as a fixup to "mips: add MSA
register definitions & access".
---
arch/mips/include/asm/msa.h | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/mips/include/asm/msa.h b/arch/mips/include/asm/msa.h
index d7fd8e1..a2aba6c 100644
--- a/arch/mips/include/asm/msa.h
+++ b/arch/mips/include/asm/msa.h
@@ -17,14 +17,18 @@ extern void _restore_msa(struct task_struct *);
static inline void enable_msa(void)
{
- if (cpu_has_msa)
+ if (cpu_has_msa) {
set_c0_config5(MIPS_CONF5_MSAEN);
+ enable_fpu_hazard();
+ }
}
static inline void disable_msa(void)
{
- if (cpu_has_msa)
+ if (cpu_has_msa) {
clear_c0_config5(MIPS_CONF5_MSAEN);
+ disable_fpu_hazard();
+ }
}
static inline int is_msa_enabled(void)
--
1.8.5.3
