Re: [PATCH 02/18] MIPS: ralink: fix RT305x clock setup

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On 10 April 2013 13:47, John Crispin <blogic@xxxxxxxxxxx> wrote:
> Add a few missing clocks and remove the unused sys clock.

You are not removing anything here, only adding ;-)

>
> Signed-off-by: John Crispin <blogic@xxxxxxxxxxx>
> ---
>  arch/mips/ralink/rt305x.c |   14 ++++++++++++++
>  1 file changed, 14 insertions(+)
>
> diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
> index 0a4bbdc..856ebff 100644
> --- a/arch/mips/ralink/rt305x.c
> +++ b/arch/mips/ralink/rt305x.c
> @@ -125,6 +125,7 @@ void __init ralink_clk_init(void)
>  {
>         unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
>         u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
> +       int wmac_20mhz = 0;
>
>         if (soc_is_rt305x() || soc_is_rt3350()) {
>                 t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
> @@ -176,11 +177,24 @@ void __init ralink_clk_init(void)
>                 BUG();
>         }
>
> +       if (soc_is_rt3352() || soc_is_rt5350()) {
> +               u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);

Empty line missing.

> +               if ((val & RT3352_CLKCFG0_XTAL_SEL) == 0)
> +                       wmac_20mhz = 1;

Why not just call it wmac_rate, default to 40000000, and set it to
20000000 here?

> +       }
> +
>         ralink_clk_add("cpu", cpu_rate);
>         ralink_clk_add("10000b00.spi", sys_rate);
>         ralink_clk_add("10000100.timer", wdt_rate);
> +       ralink_clk_add("10000120.watchdog", wdt_rate);
>         ralink_clk_add("10000500.uart", uart_rate);
>         ralink_clk_add("10000c00.uartlite", uart_rate);
> +       ralink_clk_add("10100000.ethernet", sys_rate);
> +
> +       if (wmac_20mhz)
> +               ralink_clk_add("wmac@10180000", 20000000);
> +       else
> +               ralink_clk_add("wmac@10180000", 40000000);
>  }

Then you wouldn't need the conditional here.


Jonas


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