Re: [PATCH 1/4] MIPS: Add base architecture support for RI and XI.

[David Daney <ddaney.cavm@xxxxxxxxx>]

On 09/05/2012 01:27 PM, Steven J. Hill wrote:
> From: "Steven J. Hill" <sjhill@xxxxxxxx>
>
> Originally both Read Inhibit (RI) and Execute Inhibit (XI) were
> supported by the TLB only for a SmartMIPS core. The MIPSr3(TM)
> Architecture now defines an optional feature to implement these
> TLB bits separately. Support for one or both features can be
> checked by looking at the Config3.RXI bit.
>
> Signed-off-by: Steven J. Hill <sjhill@xxxxxxxx>

This particular patch seems fine.

Acked-by: David Daney <david.daney@xxxxxxxxxx>


However in order not to break things there has to be a follow-on patch 
that is applied before any of the subsequent patches that sets 
cpu_has_ri and cpu_has_xi to the proper values for OCTEON.

David Daney


> ---
>   arch/mips/include/asm/cpu-features.h |    6 ++++++
>   arch/mips/include/asm/cpu.h          |    2 ++
>   arch/mips/include/asm/mipsregs.h     |    1 +
>   arch/mips/kernel/cpu-probe.c         |   12 +++++++++++-
>   4 files changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
> index 080edd8..c78a77b 100644
> --- a/arch/mips/include/asm/cpu-features.h
> +++ b/arch/mips/include/asm/cpu-features.h
> @@ -98,6 +98,12 @@
>   #ifndef kernel_uses_smartmips_rixi
>   #define kernel_uses_smartmips_rixi 0
>   #endif
> +#ifndef cpu_has_ri
> +#define cpu_has_ri		(cpu_data[0].options & MIPS_CPU_RI)
> +#endif
> +#ifndef cpu_has_xi
> +#define cpu_has_xi		(cpu_data[0].options & MIPS_CPU_XI)
> +#endif
>   #ifndef cpu_has_mmips
>   #define cpu_has_mmips		(cpu_data[0].options & MIPS_CPU_MICROMIPS)
>   #endif
> diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
> index 4889fae..1b928ed 100644
> --- a/arch/mips/include/asm/cpu.h
> +++ b/arch/mips/include/asm/cpu.h
> @@ -323,6 +323,8 @@ enum cpu_type_enum {
>   #define MIPS_CPU_VEIC		0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
>   #define MIPS_CPU_ULRI		0x00200000 /* CPU has ULRI feature */
>   #define MIPS_CPU_MICROMIPS	0x01000000 /* CPU has microMIPS capability */
> +#define MIPS_CPU_RI		0x02000000 /* CPU has TLB Read Inhibit */
> +#define MIPS_CPU_XI		0x04000000 /* CPU has TLB Execute Inhibit */
>
>   /*
>    * CPU ASE encodings
> diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
> index cdb9c87..19430fb 100644
> --- a/arch/mips/include/asm/mipsregs.h
> +++ b/arch/mips/include/asm/mipsregs.h
> @@ -591,6 +591,7 @@
>   #define MIPS_CONF3_LPA		(_ULCAST_(1) <<  7)
>   #define MIPS_CONF3_DSP		(_ULCAST_(1) << 10)
>   #define MIPS_CONF3_DSP2P	(_ULCAST_(1) << 11)
> +#define MIPS_CONF3_RXI		(_ULCAST_(1) << 12)
>   #define MIPS_CONF3_ULRI		(_ULCAST_(1) << 13)
>   #define MIPS_CONF3_ISA		(_ULCAST_(3) << 14)
>   #define MIPS_CONF3_ISA_OE	(_ULCAST_(1) << 16)
> diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
> index 009fc13..e85d732 100644
> --- a/arch/mips/kernel/cpu-probe.c
> +++ b/arch/mips/kernel/cpu-probe.c
> @@ -422,8 +422,18 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
>
>   	config3 = read_c0_config3();
>
> -	if (config3 & MIPS_CONF3_SM)
> +	if (config3 & MIPS_CONF3_SM) {
>   		c->ases |= MIPS_ASE_SMARTMIPS;
> +		c->options |= MIPS_CPU_RI;
> +		c->options |= MIPS_CPU_XI;
> +	}
> +	if (config3 & MIPS_CONF3_RXI) {
> +		write_c0_pagegrain(read_c0_pagegrain() | PG_RIE | PG_XIE);
> +		if (read_c0_pagegrain() & PG_RIE)
> +			c->options |= MIPS_CPU_RI;
> +		if (read_c0_pagegrain() & PG_XIE)
> +			c->options |= MIPS_CPU_XI;
> +	}
>   	if (config3 & MIPS_CONF3_DSP)
>   		c->ases |= MIPS_ASE_DSP;
>   	if (config3 & MIPS_CONF3_DSP2P)