The last 12 bits of the PCIe hardware swap size and limit registers are significant, while the same bits of the bridge PCIe registers are 0. So, to program limits correctly, we need to set the last 12 bits of the value read from the bridge limit registers to 1 before writing to the PCIe limit registers. Signed-off-by: Jayachandran C <jayachandranc@xxxxxxxxxxxxxxxxx> --- arch/mips/pci/pci-xlp.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/mips/pci/pci-xlp.c b/arch/mips/pci/pci-xlp.c index 3e177e9..140557a 100644 --- a/arch/mips/pci/pci-xlp.c +++ b/arch/mips/pci/pci-xlp.c @@ -213,13 +213,14 @@ static int xlp_enable_pci_bswap(void) nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_BASE, reg); reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEMEM_LIMIT0 + i); - nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_LIM, reg); + nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_LIM, + reg | 0xfff); reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_BASE0 + i); nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_BASE, reg); reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_LIMIT0 + i); - nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_LIM, reg); + nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff); } return 0; } -- 1.7.9.5
