On Fri, Jun 22, 2012 at 11:39:19AM +0200, Arnaud Patard wrote: > > --- a/drivers/gpu/drm/drm_vm.c > > +++ b/drivers/gpu/drm/drm_vm.c > > @@ -62,7 +62,7 @@ static pgprot_t drm_io_prot(uint32_t map_type, struct vm_area_struct *vma) > > tmp = pgprot_writecombine(tmp); > > else > > tmp = pgprot_noncached(tmp); > > -#elif defined(__sparc__) || defined(__arm__) > > +#elif defined(__sparc__) || defined(__arm__) || defined(__mips__) > > tmp = pgprot_noncached(tmp); > > btw, would it be a good idea to use uncached accelerated instead ? Not unconditionally. Only some MIPS cores support uncached accelerated. Basically you can only assume that cache modes 2 (uncached) (3 cachable non-coherent) are supported. On a SMP system use of 2 and 3 may be unwise (SGI IP27 and IP35 may throw obscure exceptions to indicate their dislike of these.) and on multi-processor systems there is mode 5, which is cachable coherent. The necessary logic is too complex to got into drm_io_prot() which already is an #ifdef mess anyway so that function should be changed to call some sort of architecutre specific hook so that function should be changed to call some sort of architecture specific hook... Ralf
