On Mon, May 21, 2012 at 10:33:32AM -0500, Steven J. Hill wrote: > Signed-off-by: Steven J. Hill <sjhill@xxxxxxxx> > --- > arch/mips/mm/c-r4k.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c > index 18546fa..bca1447 100644 > --- a/arch/mips/mm/c-r4k.c > +++ b/arch/mips/mm/c-r4k.c > @@ -1000,7 +1000,7 @@ static void __cpuinit probe_pcache(void) > c->icache.linesz = 2 << lsize; > else > c->icache.linesz = lsize; > - c->icache.sets = 64 << ((config1 >> 22) & 7); > + c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); > c->icache.ways = 1 + ((config1 >> 16) & 7); > > icache_size = c->icache.sets * > @@ -1020,7 +1020,7 @@ static void __cpuinit probe_pcache(void) > c->dcache.linesz = 2 << lsize; > else > c->dcache.linesz= lsize; > - c->dcache.sets = 64 << ((config1 >> 13) & 7); > + c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); > c->dcache.ways = 1 + ((config1 >> 7) & 7); > > dcache_size = c->dcache.sets * Good catch. I'm amazed how long we were able to get away with this bug. I guess it only covers a rather esotheric cache configuration. I wonder what variant of the 4Kc is affected by this? So far none has an I-cache with only 32 lines per way. Ralf
