Remove the loop in the cascade handler and instead unconditionally handle just the first set interrupt coming from the CPLD. This gets rid of a lot of spurious interrupts being triggered for the SMSC91111 ethernet chip especially under high(er) IDE load: "eth0: spurious interrupt (mask = 0xb3)" Verified on DB1200 and DB1300. Signed-off-by: Manuel Lauss <manuel.lauss@xxxxxxxxxxxxxx> --- arch/mips/alchemy/devboards/bcsr.c | 5 +---- 1 files changed, 1 insertions(+), 4 deletions(-) diff --git a/arch/mips/alchemy/devboards/bcsr.c b/arch/mips/alchemy/devboards/bcsr.c index 1e83ce2..f2039ef 100644 --- a/arch/mips/alchemy/devboards/bcsr.c +++ b/arch/mips/alchemy/devboards/bcsr.c @@ -90,10 +90,7 @@ static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d) unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT); disable_irq_nosync(irq); - - for ( ; bisr; bisr &= bisr - 1) - generic_handle_irq(bcsr_csc_base + __ffs(bisr)); - + generic_handle_irq(bcsr_csc_base + __ffs(bisr)); enable_irq(irq); } -- 1.7.8.4
