On Thu, Dec 01, 2011 at 09:51:17AM -0800, David Daney wrote: > The existing code breaks devices that are capable of large PCIe > transfers (Silicon Image SATA controllers for example). We don't have > code to properly determine the maximum payload size on a per-bus > basis, so the easiest thing to do is just have all devices use the > default (128). Folded into 53ba9ae0 [MIPS: Octeon: Update PCI Latency timer, PCIe payload, and PCIe max read to allow larger transactions]. Thanks, Ralf
