From: David Daney <david.daney@xxxxxxxxxx>
The existing code breaks devices that are capable of large PCIe
transfers (Silicon Image SATA controllers for example). We don't have
code to properly determine the maximum payload size on a per-bus
basis, so the easiest thing to do is just have all devices use the
default (128).
Signed-off-by: David Daney <david.daney@xxxxxxxxxx>
---
arch/mips/pci/pci-octeon.c | 10 ----------
1 files changed, 0 insertions(+), 10 deletions(-)
diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c
index e2ca7de..52a1ba7 100644
--- a/arch/mips/pci/pci-octeon.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -119,22 +119,12 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
/* Enable the PCIe normal error reporting */
pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
if (pos) {
- pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &dconfig);
/* Update Device Control */
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config);
config |= PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */
config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */
config |= PCI_EXP_DEVCTL_FERE; /* Fatal Error Reporting */
config |= PCI_EXP_DEVCTL_URRE; /* Unsupported Request */
- /*
- * Octeon's max payload is 256 bytes. Set the device's
- * to that unless it can't go that big
- */
- if ((dconfig & PCI_EXP_DEVCAP_PAYLOAD) >= 1)
- config = (config & ~PCI_EXP_DEVCTL_PAYLOAD) | (1 << 5);
- /* Set the max read size to 4KB, Octeon's max */
- config = (config & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12);
-
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config);
}
--
1.7.2.3
