On Fri, Nov 18, 2011 at 07:12:16PM +0100, Maxime Bizon wrote: > > > > Presumably because the CPU cache line size is 16 bytes? On MIPS we > > don't set pci_dfl_cache_line_size; a patch (only compile tested) to > > pick a sane default is below. > > > > Does this work for you? > > [ 0.192000] PCI: CLS 0 bytes, default 16 > > yes it does Excellent, thanks for testing. So I also queued this one for 3.3. Ralf
