Netlogic XLR chip has multiple cores. Each core includes four integrated
hardware threads, and they share L1 data and instruction caches.
If the chip is marked to be SMT capable, scheduler then could do more, say,
idle load balancing.
Changes are now confined only to the code of XLR, and hardware is probed
to get core ID for correct setup.
[jayachandranc: simplified and adapted for new merged XLR/XLP code]
Signed-off-by: Hillf Danton <dhillf@xxxxxxxxx>
Signed-off-by: Jayachandran C <jayachandranc@xxxxxxxxxxxxxxxxx>
---
arch/mips/netlogic/common/smp.c | 11 +++++++----
1 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c
index 4657fe8..7249f93 100644
--- a/arch/mips/netlogic/common/smp.c
+++ b/arch/mips/netlogic/common/smp.c
@@ -108,9 +108,16 @@ void nlm_early_init_secondary(int cpu)
*/
static void __cpuinit nlm_init_secondary(void)
{
+ current_cpu_data.core = hard_smp_processor_id() / 4;
nlm_smp_irq_init();
}
+void nlm_prepare_cpus(unsigned int max_cpus)
+{
+ /* declare we are SMT capable */
+ smp_num_siblings = nlm_threads_per_core;
+}
+
void nlm_smp_finish(void)
{
#ifdef notyet
@@ -179,10 +186,6 @@ void __init nlm_smp_setup(void)
nlm_set_nmi_handler(nlm_boot_secondary_cpus);
}
-void nlm_prepare_cpus(unsigned int max_cpus)
-{
-}
-
static int nlm_parse_cpumask(u32 cpu_mask)
{
uint32_t core0_thr_mask, core_thr_mask;
--
1.7.4.1
