On Sat, Oct 1, 2011 at 4:18 PM, Jayachandran C. <jayachandranc@xxxxxxxxxxxxxxxxx> wrote: > On Sat, Oct 01, 2011 at 02:18:49PM +0800, Hillf Danton wrote: >> On Netlogic XLR chip two pairs of performance counter registers, >> >> perf_ctrl0: c0 reg 25 sel 0, perf_cntr0: c0 reg 25 sel 1 >> perf_ctrl1: c0 reg 25 sel 2, perf_cntr0: c0 reg 25 sel 3 >> >> provide a means for software to count processor events. >> >> At most 64 events can be counted, such as, >> Instruction fetched and retired, branch instructions >> Instruction and Data Cache Unit statistics >> Instruction and Data TLB statistics >> Instruction Fetch Unit statistics >> Instruction Execution Unit statistics >> Load/store Unit statistics >> Cycle Count >> >> They are activated based on the model of mips/74k, and >> any comment is appreciated. > > I have not looked at 74k, but on XLR there is only one set of perf counter > registers in a core (or 4 hardware threads). These perf counters can count > either the events on one thread or all of the threads put together. > It is encoded in the patch to count events on all threads. Yeah it is better to count events according to user's favor. Thanks Hillf
