On 09/06/2011 12:02 PM, SAURABH MALPANI wrote:
Hi David,
Thanks a bunch for clarifying this. Just to complete, I have some code
which calls CHECK_IRQ_PER_CPU(desc->status) after every time a
descriptor is created for an irq. And based on it we create either per
cpu data structures or single data structure for that particular irq.
After your clarification, I can safely create exception for
OCTEON_IRQ_MBOX0 and OCTEON_IRQ_MBOX1 as you mention that missing the
flag is just cosmetic.
Well the performance counter and timer interrupts may suffer in a
similar manner.
David Daney
Thanks again
Saurabh
On Wed, Sep 7, 2011 at 12:08 AM, David Daney<david.daney@xxxxxxxxxx> wrote:
On 09/05/2011 03:23 AM, SAURABH MALPANI wrote:
Hi,
<Re sending this because last time I am afraid I didn't hit the
correct mail filters.>
Query:
mailbox_interrupt is not registered with IRQF_PERCPU but it is
supposed to be percpu interrupt. Is that on purpose or a miss?
On Octeon the per-cpuness of a particular irq is a property of the irq
itself rather than being controlled by IRQF_PERCPU. So other than being
perhaps stylistically in poor taste, no harm is done by omitting IRQF_PERCPU
here.
I am
porting some code from x86 to octeon which requires special handling
for per cpu interrupts.
void octeon_prepare_cpus(unsigned int max_cpus)
{
cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()),
0xffffffff);
if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt,
IRQF_DISABLED,
"mailbox0", mailbox_interrupt)) {
panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n");
}
if (request_irq(OCTEON_IRQ_MBOX1, mailbox_interrupt,
IRQF_DISABLED,
"mailbox1", mailbox_interrupt)) {
panic("Cannot request_irq(OCTEON_IRQ_MBOX1)\n");
}
}
--
Saurabh
