On 08/29/2011 04:45 PM, David Daney wrote:
On 08/29/2011 04:20 PM, Edgar E. Iglesias wrote:
Hi,
Commit 362e696428590f7d0a5d0971a2d04b0372a761b8
reorders a bunch of insns to improve the flow of the pipeline but
for MT_SMTC kernels, AFAICT, the saving of CP0_STATUS seems wrong.
Indeed.
Am I missing something?
It does look like in the MIPS_MT_SMTC case we are clobbering the value
in v1.
If not here is a patch, tested with qemu.
How about the attached completely untested one instead?
Ralf,
I didn't mean to imply that Edgar's patch was not correct, it seems
likely that it is. Really either approach is fine with me.
David Daney.
.
.
.
From d0035295ae34bcf84d601b1e25e2642fe0802752 Mon Sep 17 00:00:00 2001
From: David Daney<david.daney@xxxxxxxxxx>
Date: Mon, 29 Aug 2011 16:42:12 -0700
Subject: [PATCH] MIPS: Don't clobber CP0_STATUS vaue for CONFIG_MIPS_MT_SMTC
Untested, but it looks nice.
Reported-by: Edgar E. Iglesias<edgar.iglesias@xxxxxxxxx>
Signed-off-by: David Daney<david.daney@xxxxxxxxxx>
---
arch/mips/include/asm/stackframe.h | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index 569681e..51a3a0c 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -195,9 +195,9 @@
* to cover the pipeline delay.
*/
.set mips32
- mfc0 v1, CP0_TCSTATUS
+ mfc0 k0, CP0_TCSTATUS
.set mips0
- LONG_S v1, PT_TCSTATUS(sp)
+ LONG_S k0, PT_TCSTATUS(sp)
#endif /* CONFIG_MIPS_MT_SMTC */
LONG_S $4, PT_R4(sp)
LONG_S $5, PT_R5(sp)
