Hi,
Commit 362e696428590f7d0a5d0971a2d04b0372a761b8
reorders a bunch of insns to improve the flow of the pipeline but
for MT_SMTC kernels, AFAICT, the saving of CP0_STATUS seems wrong.
Am I missing something?
If not here is a patch, tested with qemu.
Cheers
commit 1a72dd0ed0a238007d3d67c1e3a634d477527ce2
Author: Edgar E. Iglesias <edgar.iglesias@xxxxxxxxx>
Date: Tue Aug 30 01:07:15 2011 +0200
MIPS: SMTC: Correct saving of CP0_STATUS
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xxxxxxxxx>
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index b4ba244..1b8d9a0 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -189,6 +189,9 @@
LONG_S $0, PT_R0(sp)
mfc0 v1, CP0_STATUS
LONG_S $2, PT_R2(sp)
+ LONG_S $4, PT_R4(sp)
+ LONG_S $5, PT_R5(sp)
+ LONG_S v1, PT_STATUS(sp)
#ifdef CONFIG_MIPS_MT_SMTC
/*
* Ideally, these instructions would be shuffled in
@@ -199,9 +202,6 @@
.set mips0
LONG_S v1, PT_TCSTATUS(sp)
#endif /* CONFIG_MIPS_MT_SMTC */
- LONG_S $4, PT_R4(sp)
- LONG_S $5, PT_R5(sp)
- LONG_S v1, PT_STATUS(sp)
mfc0 v1, CP0_CAUSE
LONG_S $6, PT_R6(sp)
LONG_S $7, PT_R7(sp)
