Re: [PATCH 01/10] MIPS: lantiq: add initial support for Lantiq SoCs

[Daniel Schwierzeck <daniel.schwierzeck@xxxxxxxxxxxxxx>]

Hi John,

I have some additional suggestions.

2011/1/5 John Crispin <blogic@xxxxxxxxxxx>:
> Add initial support for Mips based SoCs made by Lantiq. This series will add
> support for the XWAY family.
>
> The series allows booting a minimal system using a initramfs or NOR. Missing
> drivers and support for Amazon and GPON family will be provided in a later
> series.
>
> Signed-off-by: John Crispin <blogic@xxxxxxxxxxx>
> Signed-off-by: Ralph Hempel <ralph.hempel@xxxxxxxxxx>
> Cc: linux-mips@xxxxxxxxxxxxxx
> ---
> Âarch/mips/Kbuild.platforms         |  Â1 +
> Âarch/mips/Kconfig             Â|  16 ++
> Âarch/mips/include/asm/mach-lantiq/lantiq.h | Â 48 +++++++
> Âarch/mips/include/asm/mach-lantiq/war.h  Â|  24 +++
> Âarch/mips/lantiq/Makefile         Â|  Â9 ++
> Âarch/mips/lantiq/Platform         Â|  Â7 +
> Âarch/mips/lantiq/clk.c           | Â129 +++++++++++++++++
> Âarch/mips/lantiq/clk.h           |  18 +++
> Âarch/mips/lantiq/early_printk.c      Â|  47 ++++++
> Âarch/mips/lantiq/irq.c           | Â209 ++++++++++++++++++++++++++++
> Âarch/mips/lantiq/prom.c          Â|  84 +++++++++++
> Âarch/mips/lantiq/prom.h          Â|  26 ++++
> Âarch/mips/lantiq/setup.c          |  45 ++++++
> Â13 files changed, 663 insertions(+), 0 deletions(-)
> Âcreate mode 100644 arch/mips/include/asm/mach-lantiq/lantiq.h
> Âcreate mode 100644 arch/mips/include/asm/mach-lantiq/war.h
> Âcreate mode 100644 arch/mips/lantiq/Makefile
> Âcreate mode 100644 arch/mips/lantiq/Platform
> Âcreate mode 100644 arch/mips/lantiq/clk.c
> Âcreate mode 100644 arch/mips/lantiq/clk.h
> Âcreate mode 100644 arch/mips/lantiq/early_printk.c
> Âcreate mode 100644 arch/mips/lantiq/irq.c
> Âcreate mode 100644 arch/mips/lantiq/prom.c
> Âcreate mode 100644 arch/mips/lantiq/prom.h
> Âcreate mode 100644 arch/mips/lantiq/setup.c
>
> diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
> index 78439b8..8b7c26f 100644
> --- a/arch/mips/Kbuild.platforms
> +++ b/arch/mips/Kbuild.platforms
> @@ -10,6 +10,7 @@ platforms += dec
> Âplatforms += emma
> Âplatforms += jazz
> Âplatforms += jz4740
> +platforms += lantiq
> Âplatforms += lasat
> Âplatforms += loongson
> Âplatforms += mipssim
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 913d50d..a2396f1 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -192,6 +192,22 @@ config MACH_JZ4740
> Â Â Â Âselect SYS_HAS_EARLY_PRINTK
> Â Â Â Âselect HAVE_PWM
>
> +config LANTIQ
> + Â Â Â bool "Lantiq based platforms"
> + Â Â Â select DMA_NONCOHERENT
> + Â Â Â select IRQ_CPU
> + Â Â Â select CEVT_R4K
> + Â Â Â select CSRC_R4K
> + Â Â Â select SYS_HAS_CPU_MIPS32_R1
> + Â Â Â select SYS_HAS_CPU_MIPS32_R2
> + Â Â Â select SYS_SUPPORTS_BIG_ENDIAN
> + Â Â Â select SYS_SUPPORTS_32BIT_KERNEL
> + Â Â Â select SYS_SUPPORTS_MULTITHREADING
> + Â Â Â select SYS_HAS_EARLY_PRINTK
> + Â Â Â select ARCH_REQUIRE_GPIOLIB
> + Â Â Â select SWAP_IO_SPACE
> + Â Â Â select BOOT_RAW
> +
> Âconfig LASAT
> Â Â Â Âbool "LASAT Networks platforms"
> Â Â Â Âselect CEVT_R4K
> diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
> new file mode 100644
> index 0000000..54eb033
> --- /dev/null
> +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
> @@ -0,0 +1,48 @@
> +/*
> + * ÂThis program is free software; you can redistribute it and/or modify it
> + * Âunder the terms of the GNU General Public License version 2 as published
> + * Âby the Free Software Foundation.
> + *
> + * ÂCopyright (C) 2010 John Crispin <blogic@xxxxxxxxxxx>
> + */
> +
> +#ifndef _LANTIQ_H__
> +#define _LANTIQ_H__
> +
> +/* generic reg access functions */
> +#define ltq_r32(reg) Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â __raw_readl(reg)
> +#define ltq_w32(val, reg) Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â__raw_writel(val, reg)
> +#define ltq_w32_mask(clear, set, reg) Â\
> + Â Â Â ltq_w32((ltq_r32(reg) & ~clear) | set, reg)
> +
> +extern unsigned int ltq_get_cpu_ver(void);
> +extern unsigned int ltq_get_soc_type(void);
> +
> +/* clock speeds */
> +#define CLOCK_60M Â Â Â Â Â Â Â Â Â Â Â60000000
> +#define CLOCK_83M Â Â Â Â Â Â Â Â Â Â Â83333333
> +#define CLOCK_111M Â Â Â Â Â Â Â Â Â Â 111111111
> +#define CLOCK_133M Â Â Â Â Â Â Â Â Â Â 133333333
> +#define CLOCK_167M Â Â Â Â Â Â Â Â Â Â 166666667
> +#define CLOCK_200M Â Â Â Â Â Â Â Â Â Â 200000000
> +#define CLOCK_266M Â Â Â Â Â Â Â Â Â Â 266666666
> +#define CLOCK_333M Â Â Â Â Â Â Â Â Â Â 333333333
> +#define CLOCK_400M Â Â Â Â Â Â Â Â Â Â 400000000
> +
> +/* spinlock all ebu i/o */
> +extern spinlock_t ebu_lock;
> +
> +/* some irq helpers */
> +extern void ltq_disable_irq(unsigned int irq_nr);
> +extern void ltq_mask_and_ack_irq(unsigned int irq_nr);
> +extern void ltq_enable_irq(unsigned int irq_nr);
> +
> +#define IOPORT_RESOURCE_START Â Â Â Â Â0x10000000
> +#define IOPORT_RESOURCE_END Â Â Â Â Â Â0xffffffff
> +#define IOMEM_RESOURCE_START Â Â Â Â Â 0x10000000
> +#define IOMEM_RESOURCE_END Â Â Â Â Â Â 0xffffffff
> +
> +#define LTQ_FLASH_START Â Â Â Â Â Â Â Â0x10000000
> +#define LTQ_FLASH_MAX Â Â Â Â Â0x04000000
> +
> +#endif
> diff --git a/arch/mips/include/asm/mach-lantiq/war.h b/arch/mips/include/asm/mach-lantiq/war.h
> new file mode 100644
> index 0000000..01b08ef
> --- /dev/null
> +++ b/arch/mips/include/asm/mach-lantiq/war.h
> @@ -0,0 +1,24 @@
> +/*
> + * This file is subject to the terms and conditions of the GNU General Public
> + * License. ÂSee the file "COPYING" in the main directory of this archive
> + * for more details.
> + *
> + */
> +#ifndef __ASM_MIPS_MACH_LANTIQ_WAR_H
> +#define __ASM_MIPS_MACH_LANTIQ_WAR_H
> +
> +#define R4600_V1_INDEX_ICACHEOP_WAR Â Â 0
> +#define R4600_V1_HIT_CACHEOP_WAR Â Â Â Â0
> +#define R4600_V2_HIT_CACHEOP_WAR Â Â Â Â0
> +#define R5432_CP0_INTERRUPT_WAR Â Â Â Â 0
> +#define BCM1250_M3_WAR Â Â Â Â Â Â Â Â Â0
> +#define SIBYTE_1956_WAR Â Â Â Â Â Â Â Â 0
> +#define MIPS4K_ICACHE_REFILL_WAR Â Â Â Â0
> +#define MIPS_CACHE_SYNC_WAR Â Â Â Â Â Â 0
> +#define TX49XX_ICACHE_INDEX_INV_WAR Â Â 0
> +#define RM9000_CDEX_SMP_WAR Â Â Â Â Â Â 0
> +#define ICACHE_REFILLS_WORKAROUND_WAR Â 0
> +#define R10000_LLSC_WAR Â Â Â Â Â Â Â Â 0
> +#define MIPS34K_MISSED_ITLB_WAR Â Â Â Â 0
> +
> +#endif
> diff --git a/arch/mips/lantiq/Makefile b/arch/mips/lantiq/Makefile
> new file mode 100644
> index 0000000..6a30de6
> --- /dev/null
> +++ b/arch/mips/lantiq/Makefile
> @@ -0,0 +1,9 @@
> +# Copyright (C) 2010 John Crispin <blogic@xxxxxxxxxxx>
> +#
> +# This program is free software; you can redistribute it and/or modify it
> +# under the terms of the GNU General Public License version 2 as published
> +# by the Free Software Foundation.
> +
> +obj-y := irq.o setup.o clk.o prom.o
> +
> +obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
> diff --git a/arch/mips/lantiq/Platform b/arch/mips/lantiq/Platform
> new file mode 100644
> index 0000000..eef587f
> --- /dev/null
> +++ b/arch/mips/lantiq/Platform
> @@ -0,0 +1,7 @@
> +#
> +# Lantiq
> +#
> +
> +platform-$(CONFIG_LANTIQ) Â Â Â+= lantiq/
> +cflags-$(CONFIG_LANTIQ) Â Â Â Â Â Â Â Â+= -I$(srctree)/arch/mips/include/asm/mach-lantiq
> +load-$(CONFIG_LANTIQ) Â Â Â Â Â= 0xffffffff80002000
> diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c
> new file mode 100644
> index 0000000..4283d92
> --- /dev/null
> +++ b/arch/mips/lantiq/clk.c
> @@ -0,0 +1,129 @@
> +/*
> + * ÂThis program is free software; you can redistribute it and/or modify it
> + * Âunder the terms of the GNU General Public License version 2 as published
> + * Âby the Free Software Foundation.
> + *
> + * Copyright (C) 2010 Thomas Langer <thomas.langer@xxxxxxxxxx>
> + * Copyright (C) 2010 John Crispin <blogic@xxxxxxxxxxx>
> + */
> +
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/init.h>
> +#include <linux/kernel.h>
> +#include <linux/types.h>
> +#include <linux/clk.h>
> +#include <linux/err.h>
> +#include <linux/list.h>
> +
> +#include <asm/time.h>
> +#include <asm/irq.h>
> +#include <asm/div64.h>
> +
> +#include <lantiq.h>
> +
> +#include "clk.h"
> +
> +struct clk {
> + Â Â Â const char *name;
> + Â Â Â unsigned long rate;
> + Â Â Â unsigned long (*get_rate) (void);
> +};
> +
> +static struct clk *cpu_clk;
> +static int cpu_clk_cnt;
> +
> +static unsigned int r4k_offset;
> +static unsigned int r4k_cur;

What is the sense of these variables? They are never really used.

> +
> +static struct clk cpu_clk_generic[] = {
> + Â Â Â {
> + Â Â Â Â Â Â Â .name = "cpu",
> + Â Â Â Â Â Â Â .get_rate = ltq_get_cpu_hz,
> + Â Â Â }, {
> + Â Â Â Â Â Â Â .name = "fpi",
> + Â Â Â Â Â Â Â .get_rate = ltq_get_fpi_hz,
> + Â Â Â }, {
> + Â Â Â Â Â Â Â .name = "io",
> + Â Â Â Â Â Â Â .get_rate = ltq_get_io_region_clock,
> + Â Â Â },
> +};
> +
> +void
> +clk_init(void)
> +{
> + Â Â Â int i;
> + Â Â Â cpu_clk = cpu_clk_generic;
> + Â Â Â cpu_clk_cnt = ARRAY_SIZE(cpu_clk_generic);
> + Â Â Â for (i = 0; i < cpu_clk_cnt; i++)
> + Â Â Â Â Â Â Â printk(KERN_INFO "%s: %ld\n",
> + Â Â Â Â Â Â Â Â Â Â Â cpu_clk[i].name, clk_get_rate(&cpu_clk[i]));
> +}
> +
> +static inline int
> +clk_good(struct clk *clk)
> +{
> + Â Â Â return clk && !IS_ERR(clk);
> +}
> +
> +unsigned long
> +clk_get_rate(struct clk *clk)
> +{
> + Â Â Â if (unlikely(!clk_good(clk)))
> + Â Â Â Â Â Â Â return 0;
> +
> + Â Â Â if (clk->rate != 0)
> + Â Â Â Â Â Â Â return clk->rate;
> +
> + Â Â Â if (clk->get_rate != NULL)
> + Â Â Â Â Â Â Â return clk->get_rate();
> +
> + Â Â Â return 0;
> +}
> +EXPORT_SYMBOL(clk_get_rate);
> +
> +struct clk*
> +clk_get(struct device *dev, const char *id)
> +{
> + Â Â Â int i;
> + Â Â Â for (i = 0; i < cpu_clk_cnt; i++)
> + Â Â Â Â Â Â Â if (!strcmp(id, cpu_clk[i].name))
> + Â Â Â Â Â Â Â Â Â Â Â return &cpu_clk[i];
> + Â Â Â BUG();
> + Â Â Â return ERR_PTR(-ENOENT);
> +}
> +EXPORT_SYMBOL(clk_get);
> +
> +void
> +clk_put(struct clk *clk)
> +{
> + Â Â Â /* not used */
> +}
> +EXPORT_SYMBOL(clk_put);
> +
> +static inline u32
> +ltq_get_counter_resolution(void)
> +{
> + Â Â Â u32 res;
> + Â Â Â __asm__ __volatile__(
> +        ".set  push\n"
> +        ".set  mips32r2\n"
> +        ".set  noreorder\n"
> + Â Â Â Â Â Â Â "rdhwr Â%0, $3\n"
> + Â Â Â Â Â Â Â "ehb\n"
> + Â Â Â Â Â Â Â ".set pop\n"
> + Â Â Â Â Â Â Â : "=&r" (res)
> + Â Â Â Â Â Â Â : /* no input */
> + Â Â Â Â Â Â Â : "memory");
> + Â Â Â instruction_hazard();
> + Â Â Â return res;
> +}
> +
> +void __init
> +plat_time_init(void)
> +{
> + Â Â Â struct clk *clk = clk_get(0, "cpu");
> + Â Â Â mips_hpt_frequency = clk_get_rate(clk) / ltq_get_counter_resolution();
> + Â Â Â r4k_cur = (read_c0_count() + r4k_offset);
> + Â Â Â write_c0_compare(r4k_cur);

Like stated above the r4k_cur and r4k_offset are only initailied with
0. So the last two lines
could be written as write_c0_compare(read_c0_count()) and are actually
ineffective.

> +}
> diff --git a/arch/mips/lantiq/clk.h b/arch/mips/lantiq/clk.h
> new file mode 100644
> index 0000000..3328925
> --- /dev/null
> +++ b/arch/mips/lantiq/clk.h
> @@ -0,0 +1,18 @@
> +/*
> + * ÂThis program is free software; you can redistribute it and/or modify it
> + * Âunder the terms of the GNU General Public License version 2 as published
> + * Âby the Free Software Foundation.
> + *
> + * Copyright (C) 2010 John Crispin <blogic@xxxxxxxxxxx>
> + */
> +
> +#ifndef _LTQ_CLK_H__
> +#define _LTQ_CLK_H__
> +
> +extern void clk_init(void);
> +
> +extern unsigned long ltq_get_cpu_hz(void);
> +extern unsigned long ltq_get_fpi_hz(void);
> +extern unsigned long ltq_get_io_region_clock(void);
> +
> +#endif
> diff --git a/arch/mips/lantiq/early_printk.c b/arch/mips/lantiq/early_printk.c
> new file mode 100644
> index 0000000..0aaf4f7
> --- /dev/null
> +++ b/arch/mips/lantiq/early_printk.c
> @@ -0,0 +1,47 @@
> +/*
> + * ÂThis program is free software; you can redistribute it and/or modify it
> + * Âunder the terms of the GNU General Public License version 2 as published
> + * Âby the Free Software Foundation.
> + *
> + * ÂCopyright (C) 2010 John Crispin <blogic@xxxxxxxxxxx>
> + */
> +
> +#include <linux/init.h>
> +#include <linux/cpu.h>
> +
> +#include <lantiq.h>
> +#include <lantiq_soc.h>
> +
> +#define LTQ_ASC_BASE Â Â Â Â Â Â Â Â Â KSEG1ADDR(LTQ_ASC1_BASE)
> +#define ASC_BUF Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â1024
> +#define LTQ_ASC_FSTAT Â Â Â Â Â((u32 *)(LTQ_ASC_BASE + 0x0048))
> +#define LTQ_ASC_TBUF Â Â Â Â Â Â Â Â Â ((u32 *)(LTQ_ASC_BASE + 0x0020))
> +#define TXMASK Â Â Â Â Â Â Â Â Â Â Â Â 0x3F00
> +#define TXOFFSET Â Â Â Â Â Â Â Â Â Â Â 8
> +
> +void
> +prom_putchar(char c)
> +{
> + Â Â Â unsigned long flags;
> + Â Â Â local_irq_save(flags);
> + Â Â Â do { } while ((ltq_r32(LTQ_ASC_FSTAT) & TXMASK) >> TXOFFSET);
> + Â Â Â if (c == '\n')
> + Â Â Â Â Â Â Â ltq_w32('\r', LTQ_ASC_TBUF);
> + Â Â Â ltq_w32(c, LTQ_ASC_TBUF);
> + Â Â Â local_irq_restore(flags);
> +}
> +
> +void
> +early_printf(const char *fmt, ...)
> +{
> + Â Â Â char buf[ASC_BUF];
> + Â Â Â va_list args;
> + Â Â Â int l;
> + Â Â Â char *p, *buf_end;
> + Â Â Â va_start(args, fmt);
> + Â Â Â l = vsnprintf(buf, ASC_BUF, fmt, args);
> + Â Â Â va_end(args);
> + Â Â Â buf_end = buf + l;
> + Â Â Â for (p = buf; p < buf_end; p++)
> + Â Â Â Â Â Â Â prom_putchar(*p);
> +}

With CONFIG_EARLY_PRINTK enabled and prom_putchar() implemented you
can use printk() everywhere.
So an own early_printf() is not needed.

> diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
> new file mode 100644
> index 0000000..b1535ee
> --- /dev/null
> +++ b/arch/mips/lantiq/irq.c
> @@ -0,0 +1,209 @@
> +/*
> + * ÂThis program is free software; you can redistribute it and/or modify it
> + * Âunder the terms of the GNU General Public License version 2 as published
> + * Âby the Free Software Foundation.
> + *
> + * Copyright (C) 2010 John Crispin <blogic@xxxxxxxxxxx>
> + * Copyright (C) 2010 Thomas Langer <thomas.langer@xxxxxxxxxx>
> + */
> +
> +#include <linux/module.h>
> +#include <linux/interrupt.h>
> +
> +#include <asm/bootinfo.h>
> +#include <asm/irq_cpu.h>
> +
> +#include <lantiq.h>
> +#include <irq.h>
> +
> +#define LTQ_ICU_BASE_ADDR Â Â Â(KSEG1 | 0x1F880200)
> +
> +#define LTQ_ICU_IM0_ISR Â Â Â Â Â Â Â Â((u32 *)(LTQ_ICU_BASE_ADDR + 0x0000))
> +#define LTQ_ICU_IM0_IER Â Â Â Â Â Â Â Â((u32 *)(LTQ_ICU_BASE_ADDR + 0x0008))
> +#define LTQ_ICU_IM0_IOSR Â Â Â Â Â Â Â ((u32 *)(LTQ_ICU_BASE_ADDR + 0x0010))
> +#define LTQ_ICU_IM0_IRSR Â Â Â Â Â Â Â ((u32 *)(LTQ_ICU_BASE_ADDR + 0x0018))
> +#define LTQ_ICU_IM0_IMR Â Â Â Â Â Â Â Â((u32 *)(LTQ_ICU_BASE_ADDR + 0x0020))
> +
> +#define LTQ_ICU_IM1_ISR Â Â Â Â Â Â Â Â((u32 *)(LTQ_ICU_BASE_ADDR + 0x0028))
> +#define LTQ_ICU_IM2_ISR Â Â Â Â Â Â Â Â((u32 *)(LTQ_ICU_BASE_ADDR + 0x0050))
> +#define LTQ_ICU_IM3_ISR Â Â Â Â Â Â Â Â((u32 *)(LTQ_ICU_BASE_ADDR + 0x0078))
> +#define LTQ_ICU_IM4_ISR Â Â Â Â Â Â Â Â((u32 *)(LTQ_ICU_BASE_ADDR + 0x00A0))
> +
> +#define LTQ_ICU_OFFSET Â Â Â Â (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR)
> +
> +void
> +ltq_disable_irq(unsigned int irq_nr)
> +{
> + Â Â Â u32 *ier = LTQ_ICU_IM0_IER;
> + Â Â Â irq_nr -= INT_NUM_IRQ0;
> + Â Â Â ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
> + Â Â Â irq_nr %= INT_NUM_IM_OFFSET;
> + Â Â Â ltq_w32(ltq_r32(ier) & ~(1 << irq_nr), ier);
> +}
> +EXPORT_SYMBOL(ltq_disable_irq);
> +
> +void
> +ltq_mask_and_ack_irq(unsigned int irq_nr)
> +{
> + Â Â Â u32 *ier = LTQ_ICU_IM0_IER;
> + Â Â Â u32 *isr = LTQ_ICU_IM0_ISR;
> + Â Â Â irq_nr -= INT_NUM_IRQ0;
> + Â Â Â ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
> + Â Â Â isr += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
> + Â Â Â irq_nr %= INT_NUM_IM_OFFSET;
> + Â Â Â ltq_w32(ltq_r32(ier) & ~(1 << irq_nr), ier);
> + Â Â Â ltq_w32((1 << irq_nr), isr);
> +}
> +EXPORT_SYMBOL(ltq_mask_and_ack_irq);
> +
> +static void
> +ltq_ack_irq(unsigned int irq_nr)
> +{
> + Â Â Â u32 *isr = LTQ_ICU_IM0_ISR;
> + Â Â Â irq_nr -= INT_NUM_IRQ0;
> + Â Â Â isr += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
> + Â Â Â irq_nr %= INT_NUM_IM_OFFSET;
> + Â Â Â ltq_w32((1 << irq_nr), isr);
> +}
> +
> +void
> +ltq_enable_irq(unsigned int irq_nr)
> +{
> + Â Â Â u32 *ier = LTQ_ICU_IM0_IER;
> + Â Â Â irq_nr -= INT_NUM_IRQ0;
> + Â Â Â ier += LTQ_ICU_OFFSET Â* (irq_nr / INT_NUM_IM_OFFSET);
> + Â Â Â irq_nr %= INT_NUM_IM_OFFSET;
> + Â Â Â ltq_w32(ltq_r32(ier) | (1 << irq_nr), ier);
> +}
> +EXPORT_SYMBOL(ltq_enable_irq);
> +
> +static unsigned int
> +ltq_startup_irq(unsigned int irq)
> +{
> + Â Â Â ltq_enable_irq(irq);
> + Â Â Â return 0;
> +}
> +
> +static void
> +ltq_end_irq(unsigned int irq)
> +{
> + Â Â Â if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
> + Â Â Â Â Â Â Â ltq_enable_irq(irq);
> +}
> +
> +static struct irq_chip
> +ltq_irq_type = {
> + Â Â Â "ltq_irq",
> + Â Â Â .startup = ltq_startup_irq,
> + Â Â Â .enable = ltq_enable_irq,
> + Â Â Â .disable = ltq_disable_irq,
> + Â Â Â .unmask = ltq_enable_irq,
> + Â Â Â .ack = ltq_ack_irq,
> + Â Â Â .mask = ltq_disable_irq,
> + Â Â Â .mask_ack = ltq_mask_and_ack_irq,
> + Â Â Â .end = ltq_end_irq,
> +};
> +
> +static void
> +ltq_hw_irqdispatch(int module)
> +{
> + Â Â Â u32 irq;
> +
> + Â Â Â irq = ltq_r32(LTQ_ICU_IM0_IOSR + (module * LTQ_ICU_OFFSET));
> + Â Â Â if (irq == 0)
> + Â Â Â Â Â Â Â return;
> +
> + Â Â Â /* silicon bug causes only the msb set to 1 to be valid. all
> + Â Â Â Â Âother bits might be bogus */
> + Â Â Â irq = __fls(irq);
> + Â Â Â do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
> +}
> +
> +#define DEFINE_HWx_IRQDISPATCH(x) \
> +static void ltq_hw ## x ## _irqdispatch(void)\
> +{\
> + Â Â Â ltq_hw_irqdispatch(x); \
> +}
> +DEFINE_HWx_IRQDISPATCH(0)
> +DEFINE_HWx_IRQDISPATCH(1)
> +DEFINE_HWx_IRQDISPATCH(2)
> +DEFINE_HWx_IRQDISPATCH(3)
> +DEFINE_HWx_IRQDISPATCH(4)

The interrupt line IM0-IRL22 is shared by PCI (INT A) and EBU. Thus
ltq_hw0_irqdispatch()
should clear the PCI bit (5th bit) in EBU_PCC_ISTAT register (EBU_BASE
+ 0xA0) if you enable
this interrupt in pcibios_plat_dev_init().
This is undocumented in the hardware manuals but can be found in all
Lantiq BSP's.

> +
> +static void ltq_hw5_irqdispatch(void)
> +{
> + Â Â Â do_IRQ(MIPS_CPU_TIMER_IRQ);
> +}
> +
> +asmlinkage void
> +plat_irq_dispatch(void)
> +{
> + Â Â Â unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
> + Â Â Â unsigned int i;
> +
> + Â Â Â if (pending & CAUSEF_IP7) {
> + Â Â Â Â Â Â Â do_IRQ(MIPS_CPU_TIMER_IRQ);
> + Â Â Â Â Â Â Â goto out;
> + Â Â Â } else {
> + Â Â Â Â Â Â Â for (i = 0; i < 5; i++) {
> + Â Â Â Â Â Â Â Â Â Â Â if (pending & (CAUSEF_IP2 << i)) {
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ltq_hw_irqdispatch(i);
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â goto out;
> + Â Â Â Â Â Â Â Â Â Â Â }
> + Â Â Â Â Â Â Â }
> + Â Â Â }
> + Â Â Â printk(KERN_ALERT "Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
> +
> +out:
> + Â Â Â return;
> +}
> +
> +static struct irqaction
> +cascade = {
> + Â Â Â .handler = no_action,
> + Â Â Â .flags = IRQF_DISABLED,
> + Â Â Â .name = "cascade",
> +};
> +
> +void __init
> +arch_init_irq(void)
> +{
> + Â Â Â int i;
> +
> + Â Â Â for (i = 0; i < 5; i++)
> + Â Â Â Â Â Â Â ltq_w32(0, LTQ_ICU_IM0_IER + (i * LTQ_ICU_OFFSET));

Perhaps pending interrupts should be cleared too with
ltq_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET));

> +
> + Â Â Â mips_cpu_irq_init();
> +
> + Â Â Â for (i = 2; i <= 6; i++)
> + Â Â Â Â Â Â Â setup_irq(i, &cascade);
> +
> + Â Â Â if (cpu_has_vint) {
> + Â Â Â Â Â Â Â printk(KERN_INFO "Setting up vectored interrupts\n");
> + Â Â Â Â Â Â Â set_vi_handler(2, ltq_hw0_irqdispatch);
> + Â Â Â Â Â Â Â set_vi_handler(3, ltq_hw1_irqdispatch);
> + Â Â Â Â Â Â Â set_vi_handler(4, ltq_hw2_irqdispatch);
> + Â Â Â Â Â Â Â set_vi_handler(5, ltq_hw3_irqdispatch);
> + Â Â Â Â Â Â Â set_vi_handler(6, ltq_hw4_irqdispatch);
> + Â Â Â Â Â Â Â set_vi_handler(7, ltq_hw5_irqdispatch);
> + Â Â Â }
> +
> + Â Â Â for (i = INT_NUM_IRQ0;
> + Â Â Â Â Â Â Â i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++)
> + Â Â Â Â Â Â Â set_irq_chip_and_handler(i, &ltq_irq_type,
> + Â Â Â Â Â Â Â Â Â Â Â handle_level_irq);
> +
> + Â Â Â #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
> + Â Â Â set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
> + Â Â Â Â Â Â Â IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
> + Â Â Â #else
> + Â Â Â set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
> + Â Â Â Â Â Â Â IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
> + Â Â Â #endif
> +}
> +
> +unsigned int __cpuinit
> +get_c0_compare_int(void)
> +{
> + Â Â Â return CP0_LEGACY_COMPARE_IRQ;
> +}
> diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
> new file mode 100644
> index 0000000..6561e4e
> --- /dev/null
> +++ b/arch/mips/lantiq/prom.c
> @@ -0,0 +1,84 @@
> +/*
> + * ÂThis program is free software; you can redistribute it and/or modify it
> + * Âunder the terms of the GNU General Public License version 2 as published
> + * Âby the Free Software Foundation.
> + *
> + * Copyright (C) 2010 John Crispin <blogic@xxxxxxxxxxx>
> + */
> +
> +#include <linux/module.h>
> +#include <linux/clk.h>
> +#include <asm/bootinfo.h>
> +#include <asm/time.h>
> +
> +#include <lantiq.h>
> +
> +#include "prom.h"
> +#include "clk.h"
> +
> +static struct ltq_soc_info soc_info;
> +
> +/* for Multithreading (APRP) on MIPS34K */
> +unsigned long physical_memsize;
> +
> +/* all access to the ebu must be locked */
> +DEFINE_SPINLOCK(ebu_lock);
> +EXPORT_SYMBOL_GPL(ebu_lock);

This lock is only needed if you want to use software arbitration.
Normally the EBU does hardware arbitration and can be accessed safely
without lock.

> +
> +unsigned int
> +ltq_get_cpu_ver(void)
> +{
> + Â Â Â return soc_info.rev;
> +}
> +EXPORT_SYMBOL(ltq_get_cpu_ver);
> +
> +unsigned int
> +ltq_get_soc_type(void)
> +{
> + Â Â Â return soc_info.type;
> +}
> +EXPORT_SYMBOL(ltq_get_soc_type);
> +
> +const char*
> +get_system_type(void)
> +{
> + Â Â Â return soc_info.sys_type;
> +}
> +
> +void
> +prom_free_prom_memory(void)
> +{
> +}
> +
> +static void __init
> +prom_init_cmdline(void)
> +{
> + Â Â Â int argc = fw_arg0;
> + Â Â Â char **argv = (char **) KSEG1ADDR(fw_arg1);
> + Â Â Â int i;
> + Â Â Â arcs_cmdline[0] = '\0';
> + Â Â Â if (argc)
> + Â Â Â Â Â Â Â for (i = 1; i < argc; i++) {
> + Â Â Â Â Â Â Â Â Â Â Â strlcat(arcs_cmdline, (char *)KSEG1ADDR(argv[i]),
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â COMMAND_LINE_SIZE);
> + Â Â Â Â Â Â Â Â Â Â Â if (i + 1 != argc)
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
> + Â Â Â Â Â Â Â }
> + Â Â Â if (!*arcs_cmdline)
> + Â Â Â Â Â Â Â strcpy(&(arcs_cmdline[0]),
> + Â Â Â Â Â Â Â Â Â Â Â "console=ttyS1,115200 rootfstype=squashfs,jffs2");
> +}
> +
> +void __init
> +prom_init(void)
> +{
> + Â Â Â struct clk *clk;
> + Â Â Â ltq_soc_detect(&soc_info);
> + Â Â Â clk_init();
> + Â Â Â clk = clk_get(0, "cpu");
> + Â Â Â snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev1.%d %ldMhz",
> + Â Â Â Â Â Â Â soc_info.name, soc_info.rev, clk_get_rate(clk) / 1000000);
> + Â Â Â soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0';
> + Â Â Â printk(KERN_INFO "SoC: %s\n", soc_info.sys_type);
> + Â Â Â prom_init_cmdline();
> +}
> diff --git a/arch/mips/lantiq/prom.h b/arch/mips/lantiq/prom.h
> new file mode 100644
> index 0000000..3b92197
> --- /dev/null
> +++ b/arch/mips/lantiq/prom.h
> @@ -0,0 +1,26 @@
> +/*
> + * ÂThis program is free software; you can redistribute it and/or modify it
> + * Âunder the terms of the GNU General Public License version 2 as published
> + * Âby the Free Software Foundation.
> + *
> + * Copyright (C) 2010 John Crispin <blogic@xxxxxxxxxxx>
> + */
> +
> +#ifndef _LTQ_PROM_H__
> +#define _LTQ_PROM_H__
> +
> +#define LTQ_SYS_TYPE_LEN Â Â Â 0x100
> +
> +struct ltq_soc_info {
> + Â Â Â unsigned char *name;
> + Â Â Â unsigned int rev;
> + Â Â Â unsigned int partnum;
> + Â Â Â unsigned int type;
> + Â Â Â unsigned char sys_type[LTQ_SYS_TYPE_LEN];
> +};
> +
> +void ltq_soc_detect(struct ltq_soc_info *i);
> +
> +void early_printf(const char *fmt, ...);
> +
> +#endif
> diff --git a/arch/mips/lantiq/setup.c b/arch/mips/lantiq/setup.c
> new file mode 100644
> index 0000000..f0f74d2
> --- /dev/null
> +++ b/arch/mips/lantiq/setup.c
> @@ -0,0 +1,45 @@
> +/*
> + * ÂThis program is free software; you can redistribute it and/or modify it
> + * Âunder the terms of the GNU General Public License version 2 as published
> + * Âby the Free Software Foundation.
> + *
> + * Copyright (C) 2010 John Crispin <blogic@xxxxxxxxxxx>
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/io.h>
> +#include <linux/ioport.h>
> +#include <asm/bootinfo.h>
> +
> +#include <lantiq.h>
> +
> +void __init
> +plat_mem_setup(void)
> +{
> + Â Â Â /* assume 16M as default */
> + Â Â Â unsigned long memsize = 16;
> + Â Â Â char **envp = (char **) KSEG1ADDR(fw_arg2);
> + Â Â Â u32 status;
> +
> + Â Â Â /* make sure to have no "reverse endian" for user mode */
> + Â Â Â status = read_c0_status();
> + Â Â Â status &= (~(1<<25));
> + Â Â Â write_c0_status(status);
> +
> + Â Â Â ioport_resource.start = IOPORT_RESOURCE_START;
> + Â Â Â ioport_resource.end = IOPORT_RESOURCE_END;
> + Â Â Â iomem_resource.start = IOMEM_RESOURCE_START;
> + Â Â Â iomem_resource.end = IOMEM_RESOURCE_END;
> +
> + Â Â Â while (*envp) {
> + Â Â Â Â Â Â Â char *e = (char *)KSEG1ADDR(*envp);
> + Â Â Â Â Â Â Â if (!strncmp(e, "memsize=", 8)) {
> + Â Â Â Â Â Â Â Â Â Â Â e += 8;
> + Â Â Â Â Â Â Â Â Â Â Â strict_strtoul(e, 0, &memsize);
> + Â Â Â Â Â Â Â }
> + Â Â Â Â Â Â Â envp++;
> + Â Â Â }
> + Â Â Â memsize *= 1024 * 1024;
> + Â Â Â add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
> +}
> --
> 1.7.2.3
>
>
>