Re: [PATCH 2/2] MIPS: Use BBIT instructions in TLB handlers

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To: David Daney <ddaney@xxxxxxxxxxxxxxxxxx>
Subject: Re: [PATCH 2/2] MIPS: Use BBIT instructions in TLB handlers
From: Ralf Baechle <ralf@xxxxxxxxxxxxxx>
Date: Tue, 28 Dec 2010 18:00:03 +0100
Cc: linux-mips@xxxxxxxxxxxxxx
In-reply-to: <1292889290-12849-3-git-send-email-ddaney@xxxxxxxxxxxxxxxxxx>
User-agent: Mutt/1.5.21 (2010-09-15)

On Mon, Dec 20, 2010 at 03:54:50PM -0800, David Daney wrote:

> If the CPU supports BBIT0 and BBIT1, use them in TLB handlers as they
> are more efficient than an AND followed by an branch and then
> restoring the clobbered register.

Queued for 2.6.38.  Thanks,

  Ralf

References:
- [PATCH 0/2] MIPS: Use Octeon BBIT instructions in TLB handlers.
  - From: David Daney
- [PATCH 2/2] MIPS: Use BBIT instructions in TLB handlers
  - From: David Daney

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