Thanks a lot Mr. Ralf Baechle for Quick answer. I will give more info. CONFIG_MIPS_L1_CACHE_SHIFT=5 CONFIG_DMA_NONCOHERENT=y mips 34kc is processor and File we are using is arch/mips/include/asm/mach-generic/kmalloc.h #ifndef __ASM_MACH_GENERIC_KMALLOC_H #define __ASM_MACH_GENERIC_KMALLOC_H #ifndef CONFIG_DMA_COHERENT /* * Total overkill for most systems but need as a safe default. * Set this one if any device in the system might do non-coherent DMA. */ #define ARCH_KMALLOC_MINALIGN 128 #endif #endif /* __ASM_MACH_GENERIC_KMALLOC_H */ So shall we make value ARCH_KMALLOC_MINALIGN from 128 to 32. is there any problem ? Thanks On Wed, Aug 18, 2010 at 7:03 PM, Ralf Baechle <ralf@xxxxxxxxxxxxxx> wrote: > On Wed, Aug 18, 2010 at 06:07:12PM +0530, naveen yadav wrote: > >> To: majordomo@xxxxxxxxx, linux-mips@xxxxxxxxxxxxxx > > Your sentences are to complex for majordomo to understand. Also its > area of expertise is generally limited to mailing list related issues. > >> We are using MIPS(mips32r2) target. when I alloc memory using kmalloc >> suppose 28 bytes, the kernel still consume 128 bytes. >> >> So when I check File on kernel source mach-ip32/kmalloc.h >> >> Since it is allign to 128 bytes so i understand that even if I >> consume 1 byte it will waste 128 bytes. >> >> #ifndef __ASM_MACH_IP32_KMALLOC_H >> #define __ASM_MACH_IP32_KMALLOC_H > > Eh... That's an IP32-specific header. I have no idea why you're looking > at it. It's not being used for your platform. > >> So I could not understand why it is allign to 128 bytes. Is there any >> specific reason for it. ? > > Each allocation needs some memory for kmalloc's internal bookkeeping, > the memory you actually asked for and for cacheline alignment. For very > small allocations the later is likely to be larger than the other two > so will be the deciding factor in actual memory allocation. > > The cacheline aligment results in better performance and on non-coherent > platforms such as probably yours it is necessary to get get DMA transfers > to work right. > > It would appear that in your case CONFIG_MIPS_L1_CACHE_SHIFT is set to 7. > For a MIPS32-based platform (you didn' say what actual processor core!) > that appears to be an excessively large number. 32 bytes would be a more > typical figure. Just check the kernel bootup messages for the cacheline > size if you don't know. > > Ralf >
