On Wed, Feb 24, 2010 at 09:03:33AM +0900, Yoichi Yuasa wrote: > > approach Ben suggested long ago: > > http://marc.info/?l=linux-kernel&m=119733290624544&w=2 > > It works fine with 2.6.34 queue tree. > pci.c change is already committed by Ralf. Which I just dropped from queue. To keep the tree bisectable removal of the old hack and adding the fixup should be done in the same patch so I'd go for Bjorn's patch. There is another somewhat theoretical correctness issue. Because the VIA SuperIO chip only decodes 24 bits of address space but port address space currently being configured as 32MB there is the theoretical possibility of I/O port addresses that alias with legacy addresses getting allocated. The complicated solution is to reserve all address range that potencially could cause such aliases. But with the PCI spec limiting port allocations for devices to a maximum of 256 bytes 16MB of port address space already is way more than one would ever expect to be used so I suggest to just limit the port address space to 16MB. Could you test the patch below? Ralf Signed-off-by: Ralf Baechle <ralf@xxxxxxxxxxxxxx> arch/mips/cobalt/pci.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/cobalt/pci.c b/arch/mips/cobalt/pci.c index cfce7af..85ec9cc 100644 --- a/arch/mips/cobalt/pci.c +++ b/arch/mips/cobalt/pci.c @@ -25,7 +25,7 @@ static struct resource cobalt_mem_resource = { static struct resource cobalt_io_resource = { .start = 0x1000, - .end = GT_DEF_PCI0_IO_SIZE - 1, + .end = 0xffffffUL, .name = "PCI I/O", .flags = IORESOURCE_IO, };
