On Tue, 23 Feb 2010 16:01:14 -0700 Bjorn Helgaas <bjorn.helgaas@xxxxxx> wrote: > On Monday 22 February 2010 06:28:30 am Ralf Baechle wrote: > > It's a while since I last looked into this but here's how things afair > > are working on a MIPS-based Cobalt system. > > > > The system is based on a MIPS processor and a GT-64111 system controller. > > Addresses within a certain CPU address range are passed to the PCI bus as > > I/O cycles without address cycles. Since memory is starting at CPU address > > zero (and has to because of the processors used), that address window has > > to get mapped somewhere else. So a CPU access to some virtual address gets > > translated to physical address 0xf00001f0. The GT-64111 passes this to the > > PCI bus as I/O port address 0xf00001f0. Finally the VT82C586 chip which > > only decodes the low 16 bits drops treats this as an I/O port space address > > 0x1f0. > > Yoichi, can you try the patch below? I think this is basically the > approach Ben suggested long ago: > http://marc.info/?l=linux-kernel&m=119733290624544&w=2 It works fine with 2.6.34 queue tree. pci.c change is already committed by Ralf. Thanks, Yoichi
