On 02/10/2010 03:56 PM, Ralf Baechle wrote:
On Wed, Feb 10, 2010 at 03:08:33PM -0800, David Daney wrote:
This patch set adds execute and read inhibit support. By default glibc
based tool chains will create mappings for data areas of a program and
shared libraries with PROT_EXEC cleared. With this patch applied, a
SIGSEGV is correctly sent if an attempt is made to execute from data
areas.
The first three patch just make a few tweaks in preperation for the
main body of the patch in 4/6. The last two turn on the feature for
some Octeon CPUs.
I will reply with the six patches.
David Daney (6):
MIPS: Use 64-bit stores to c0_entrylo on 64-bit kernels.
MIPS: Add accessor functions and bit definitions for c0_PageGrain
MIPS: Add TLBR and ROTR to uasm.
MIPS: Implement Read Inhibit/eXecute Inhibit
MIPS: Give Octeon+ CPUs their own cputype.
MIPS: Enable Read Inhibit/eXecute Inhibit for Octeon+ CPUs
Hangs on IP27 after
[...]
Calibrating delay loop... 178.17 BogoMIPS (lpj=89088)
Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)
Try the attached patch.
David Daney
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index ec60bd5..5ea0af8 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -749,11 +749,11 @@ static void __cpuinit build_update_entries(u32 **p, unsigned int tmp,
UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
} else {
- UASM_i_SRL(p, tmp, tmp, 6); /* convert to entrylo0 */
+ UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */
if (r4k_250MHZhwbug())
UASM_i_MTC0(p, 0, C0_ENTRYLO0);
UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
- UASM_i_SRL(p, ptep, ptep, 6); /* convert to entrylo1 */
+ UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */
if (r45k_bvahwbug())
uasm_i_mfc0(p, tmp, C0_INDEX);
}
