This patch set adds execute and read inhibit support. By default glibc
based tool chains will create mappings for data areas of a program and
shared libraries with PROT_EXEC cleared. With this patch applied, a
SIGSEGV is correctly sent if an attempt is made to execute from data
areas.
The first three patch just make a few tweaks in preperation for the
main body of the patch in 4/6. The last two turn on the feature for
some Octeon CPUs.
I will reply with the six patches.
David Daney (6):
MIPS: Use 64-bit stores to c0_entrylo on 64-bit kernels.
MIPS: Add accessor functions and bit definitions for c0_PageGrain
MIPS: Add TLBR and ROTR to uasm.
MIPS: Implement Read Inhibit/eXecute Inhibit
MIPS: Give Octeon+ CPUs their own cputype.
MIPS: Enable Read Inhibit/eXecute Inhibit for Octeon+ CPUs
arch/mips/include/asm/cpu-features.h | 3 +
arch/mips/include/asm/cpu.h | 2 +-
.../asm/mach-cavium-octeon/cpu-feature-overrides.h | 3 +
arch/mips/include/asm/mipsregs.h | 11 ++
arch/mips/include/asm/pgtable-32.h | 4 +-
arch/mips/include/asm/pgtable-64.h | 4 +-
arch/mips/include/asm/pgtable-bits.h | 105 ++++++++++--
arch/mips/include/asm/pgtable.h | 26 ++-
arch/mips/include/asm/uasm.h | 4 +
arch/mips/kernel/cpu-probe.c | 6 +-
arch/mips/mm/c-octeon.c | 7 +-
arch/mips/mm/cache.c | 53 ++++--
arch/mips/mm/fault.c | 27 +++-
arch/mips/mm/init.c | 2 +-
arch/mips/mm/tlb-r4k.c | 19 ++-
arch/mips/mm/tlbex.c | 183
++++++++++++++++----
arch/mips/mm/uasm.c | 9 +-
17 files changed, 375 insertions(+), 93 deletions(-)
