On Mon, 1 Feb 2010, Guenter Roeck wrote:
> On Mon, 2010-02-01 at 16:42 -0500, David Daney wrote:
> > Guenter Roeck wrote:
> > [...]
> > >
> > > +static inline void cpu_set_vmbits(struct cpuinfo_mips *c)
> > > +{
> > > + if (cpu_has_64bits) {
> > > + unsigned long zbits;
> > > +
> > > + asm volatile(".set mips64\n"
> > > + "and %0, 0\n"
> > > + "dsubu %0, 1\n"
> > > + "dmtc0 %0, $10, 0\n"
> > > + "dmfc0 %0, $10, 0\n"
> > > + "dsll %0, %0, 2\n"
> > > + "dsra %0, %0, 2\n"
> > > + "dclz %0, %0\n"
> > > + ".set mips0\n"
> > > + : "=r" (zbits));
> > > + c->vmbits = 64 - zbits;
> > > + } else
> > > + c->vmbits = 32;
> > > +}
> > > +
> >
> > It should be possible to express this in 'pure' C using
> > read_c0_entryhi()/write_c0_entryhi(), also you need to be sure you are
>
> Sure, no problem.
Especially as:
1. DCLZ is not a valid MIPS III instruction; some 64-bit CPUs will fault
on it.
2. You have to take care of CP0 hazards, e.g. with the R4000 if an MTC0 is
immediately followed by an MFC0 accessing the same CP0 register, then
the result of the latter instruction is unpredictable.
Maciej
