From: Wu Zhangjin <wuzhangjin@xxxxxxxxx>
Because the high resolution sched_clock() for r4k has the same overflow
problem and solution mentioned in "MIPS: Octeon: Use non-overflowing
arithmetic in sched_clock".
"With typical mult and shift values, the calculation for Octeon's
sched_clock overflows when using 64-bit arithmetic. Use 128-bit
calculations instead."
To reduce the duplication, This patch abstracts the solution into an
inline funciton mips_sched_clock() into arch/mips/include/asm/time.h
from arch/mips/cavium-octeon/csrc-octeon.c.
Two patches for Cavium and R4K will be sent out respectively to use this
common function.
Signed-off-by: Wu Zhangjin <wuzhangjin@xxxxxxxxx>
---
arch/mips/include/asm/time.h | 30 ++++++++++++++++++++++++++++++
1 files changed, 30 insertions(+), 0 deletions(-)
diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h
index c7f1bfe..f7bd5ce 100644
--- a/arch/mips/include/asm/time.h
+++ b/arch/mips/include/asm/time.h
@@ -96,4 +96,34 @@ static inline void clockevent_set_clock(struct clock_event_device *cd,
clockevents_calc_mult_shift(cd, clock, 4);
}
+static inline unsigned long long mips_sched_clock(struct clocksource *cs, u64 cnt)
+{
+ /* 64-bit arithmatic can overflow, so use 128-bit. */
+#if (__GNUC__ < 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ <= 3))
+ u64 t1, t2, t3;
+ unsigned long long rv;
+ u64 mult = cs->mult;
+ u64 shift = cs->shift;
+
+ asm (
+ "dmultu\t%[cnt],%[mult]\n\t"
+ "nor\t%[t1],$0,%[shift]\n\t"
+ "mfhi\t%[t2]\n\t"
+ "mflo\t%[t3]\n\t"
+ "dsll\t%[t2],%[t2],1\n\t"
+ "dsrlv\t%[rv],%[t3],%[shift]\n\t"
+ "dsllv\t%[t1],%[t2],%[t1]\n\t"
+ "or\t%[rv],%[t1],%[rv]\n\t"
+ : [rv] "=&r" (rv), [t1] "=&r" (t1), [t2] "=&r" (t2), [t3] "=&r" (t3)
+ : [cnt] "r" (cnt), [mult] "r" (mult), [shift] "r" (shift)
+ : "hi", "lo");
+ return rv;
+#else /* GCC > 4.3 do it the easy way. */
+ unsigned int __attribute__((mode(TI))) t = cnt;
+
+ t = (t * cs->mult) >> cs->shift;
+ return (unsigned long long)t;
+#endif
+}
+
#endif /* _ASM_TIME_H */
--
1.6.6
