On Thu, 2010-01-21 at 11:57 -0800, David Daney wrote: > >> Since the current CPU sees the memory accesses in order, what can be > >> happening on other CPUs that would require a full mb()? > > > > Lets look at a hypothetical situation with: > > > > add_wait_queue(); > > current->state = TASK_UNINTERRUPTIBLE; > > smp_wmb(); > > if (!x) > > schedule(); > > > > > > > > Then somewhere we probably have: > > > > x = 1; > > smp_wmb(); > > wake_up(queue); > > > > > > > > CPU 0 CPU 1 > > ------------ ----------- > > add_wait_queue(); > > (cpu pipeline sees a load > > of x ahead, and preloads it) > > > This is what I thought. > > My cpu (Cavium Octeon) does not have out of order reads, so my wmb() is Can you have reads that are out of order wrt writes? Because the above does not have out of order reads. It just had a read that came before a write. The above code could look like: (hypothetical assembly language) ld r2, TASK_UNINTERRUPTIBLE st r2, (current->state) wmb ld r1, (x) cmp r1, 0 Is it possible for the CPU to do the load of r1 before storing r2? If so, then the bug still exists. -- Steve > in fact a full mb() from the point of view of the current CPU. So I > think I could weaken my bariers in set_current_state() and still get > correct operation. However as you say... >
