On Sun, Nov 22, 2009 at 07:08:05PM +0800, Wu Zhangjin wrote: > > > + data = (0xffffffffUL / tclk / 2 - 2) * HZ; > > Because the MIPS c0 count's frequency is half of the cpu frequency(Hi, > Ralf, does every MIPS c0 count meet this feature?), so, the above line > should be: There are processors which have no cp0 counter at all; these are mostly very old pre-R4000 era 32-bit MIPS I and MIPS II cores. Of those which have a cp0 counter most will clock it at "half the maximum instruction issue rate" and a few at the full rate. Finally for a few such as the RM52xx either half or the full count the rate is selectable by the reset initialization bitstream fed into the processor. Too make this feature suck nicely there is no way for software to find out which rate was selected so software must know that or calibrate against a timer of known frequency. Platform-specific code does this by setting mips_hpt_frequency to the count rate before calling init_r4k_clocksource; it's also the value being passed into setup_sched_clock_update() so you don't need to count for the half / full clock rate thing there. I don't see why you need the -2 in your formula so the whole thing can be simplified to: data = 0x80000000 / tclk * HZ; Ralf
