Some newer Octeon chips have registers that allow lockless operation
of the interrupt controller. Take advantage of them.
Signed-off-by: David Daney <ddaney@xxxxxxxxxxxxxxxxxx>
---
arch/mips/cavium-octeon/octeon-irq.c | 177 +++++++++++++++++++++++++++++++++-
1 files changed, 172 insertions(+), 5 deletions(-)
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index 0bda5c5..865ff7b 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -178,6 +178,50 @@ static void octeon_irq_ciu0_disable(unsigned int irq)
#endif
}
+/*
+ * Enable the irq on the current core for chips that have the EN*_W1{S,C}
+ * registers.
+ */
+static void octeon_irq_ciu0_enable_v2(unsigned int irq)
+{
+ int index = cvmx_get_core_num() * 2;
+ u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
+
+ cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
+}
+
+/*
+ * Disable the irq on the current core for chips that have the EN*_W1{S,C}
+ * registers.
+ */
+static void octeon_irq_ciu0_disable_v2(unsigned int irq)
+{
+ int index = cvmx_get_core_num() * 2;
+ u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
+
+ cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
+}
+
+/*
+ * Disable the irq on the all cores for chips that have the EN*_W1{S,C}
+ * registers.
+ */
+static void octeon_irq_ciu0_disable_all_v2(unsigned int irq)
+{
+ u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
+ int index;
+#ifdef CONFIG_SMP
+ int cpu;
+ for_each_online_cpu(cpu) {
+ index = cpu_logical_map(cpu) * 2;
+ cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
+ }
+#else
+ index = cvmx_get_core_num() * 2;
+ cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
+#endif
+}
+
#ifdef CONFIG_SMP
static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *dest)
{
@@ -205,8 +249,42 @@ static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *
return 0;
}
+
+/*
+ * Set affinity for the irq for chips that have the EN*_W1{S,C}
+ * registers.
+ */
+static int octeon_irq_ciu0_set_affinity_v2(unsigned int irq,
+ const struct cpumask *dest)
+{
+ int cpu;
+ int index;
+ u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
+ for_each_online_cpu(cpu) {
+ index = cpu_logical_map(cpu) * 2;
+ if (cpumask_test_cpu(cpu, dest))
+ cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
+ else
+ cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
+ }
+ return 0;
+}
#endif
+/*
+ * Newer octeon chips have support for lockless CIU operation.
+ */
+static struct irq_chip octeon_irq_chip_ciu0_v2 = {
+ .name = "CIU0",
+ .enable = octeon_irq_ciu0_enable_v2,
+ .disable = octeon_irq_ciu0_disable_all_v2,
+ .ack = octeon_irq_ciu0_disable_v2,
+ .eoi = octeon_irq_ciu0_enable_v2,
+#ifdef CONFIG_SMP
+ .set_affinity = octeon_irq_ciu0_set_affinity_v2,
+#endif
+};
+
static struct irq_chip octeon_irq_chip_ciu0 = {
.name = "CIU0",
.enable = octeon_irq_ciu0_enable,
@@ -296,8 +374,53 @@ static void octeon_irq_ciu1_disable(unsigned int irq)
#endif
}
+/*
+ * Enable the irq on the current core for chips that have the EN*_W1{S,C}
+ * registers.
+ */
+static void octeon_irq_ciu1_enable_v2(unsigned int irq)
+{
+ int index = cvmx_get_core_num() * 2 + 1;
+ u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
+
+ cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
+}
+
+/*
+ * Disable the irq on the current core for chips that have the EN*_W1{S,C}
+ * registers.
+ */
+static void octeon_irq_ciu1_disable_v2(unsigned int irq)
+{
+ int index = cvmx_get_core_num() * 2 + 1;
+ u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
+
+ cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
+}
+
+/*
+ * Disable the irq on the all cores for chips that have the EN*_W1{S,C}
+ * registers.
+ */
+static void octeon_irq_ciu1_disable_all_v2(unsigned int irq)
+{
+ u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
+ int index;
#ifdef CONFIG_SMP
-static int octeon_irq_ciu1_set_affinity(unsigned int irq, const struct cpumask *dest)
+ int cpu;
+ for_each_online_cpu(cpu) {
+ index = cpu_logical_map(cpu) * 2 + 1;
+ cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
+ }
+#else
+ index = cvmx_get_core_num() * 2 + 1;
+ cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
+#endif
+}
+
+#ifdef CONFIG_SMP
+static int octeon_irq_ciu1_set_affinity(unsigned int irq,
+ const struct cpumask *dest)
{
int cpu;
unsigned long flags;
@@ -324,8 +447,42 @@ static int octeon_irq_ciu1_set_affinity(unsigned int irq, const struct cpumask *
return 0;
}
+
+/*
+ * Set affinity for the irq for chips that have the EN*_W1{S,C}
+ * registers.
+ */
+static int octeon_irq_ciu1_set_affinity_v2(unsigned int irq,
+ const struct cpumask *dest)
+{
+ int cpu;
+ int index;
+ u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
+ for_each_online_cpu(cpu) {
+ index = cpu_logical_map(cpu) * 2 + 1;
+ if (cpumask_test_cpu(cpu, dest))
+ cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
+ else
+ cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
+ }
+ return 0;
+}
#endif
+/*
+ * Newer octeon chips have support for lockless CIU operation.
+ */
+static struct irq_chip octeon_irq_chip_ciu1_v2 = {
+ .name = "CIU0",
+ .enable = octeon_irq_ciu1_enable_v2,
+ .disable = octeon_irq_ciu1_disable_all_v2,
+ .ack = octeon_irq_ciu1_disable_v2,
+ .eoi = octeon_irq_ciu1_enable_v2,
+#ifdef CONFIG_SMP
+ .set_affinity = octeon_irq_ciu1_set_affinity_v2,
+#endif
+};
+
static struct irq_chip octeon_irq_chip_ciu1 = {
.name = "CIU1",
.enable = octeon_irq_ciu1_enable,
@@ -422,6 +579,8 @@ static struct irq_chip octeon_irq_chip_msi = {
void __init arch_init_irq(void)
{
int irq;
+ struct irq_chip *chip0;
+ struct irq_chip *chip1;
#ifdef CONFIG_SMP
/* Set the default affinity to the boot cpu. */
@@ -432,6 +591,16 @@ void __init arch_init_irq(void)
if (NR_IRQS < OCTEON_IRQ_LAST)
pr_err("octeon_irq_init: NR_IRQS is set too low\n");
+ if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) ||
+ OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
+ OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X)) {
+ chip0 = &octeon_irq_chip_ciu0_v2;
+ chip1 = &octeon_irq_chip_ciu1_v2;
+ } else {
+ chip0 = &octeon_irq_chip_ciu0;
+ chip1 = &octeon_irq_chip_ciu1;
+ }
+
/* 0 - 15 reserved for i8259 master and slave controller. */
/* 17 - 23 Mips internal */
@@ -442,14 +611,12 @@ void __init arch_init_irq(void)
/* 24 - 87 CIU_INT_SUM0 */
for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) {
- set_irq_chip_and_handler(irq, &octeon_irq_chip_ciu0,
- handle_percpu_irq);
+ set_irq_chip_and_handler(irq, chip0, handle_percpu_irq);
}
/* 88 - 151 CIU_INT_SUM1 */
for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_RESERVED151; irq++) {
- set_irq_chip_and_handler(irq, &octeon_irq_chip_ciu1,
- handle_percpu_irq);
+ set_irq_chip_and_handler(irq, chip1, handle_percpu_irq);
}
#ifdef CONFIG_PCI_MSI
--
1.6.0.6
