On Wed, Sep 16, 2009 at 11:09:35AM -0700, David Daney wrote: >>> According to the MIPS64 Privileged Resource Architecture manual, only >>> values of zero may be written to bits 8..10 of CP0 entryhi. We need >>> to add masking by ASID_MASK. >> >> Yes, I've silently been relying on the hardware chopping off the excess >> bits for no better reason that it saving an instruction. One of the >> functions you've touched is switch_mm() which is being used in context >> switches and any changes to it will show up in context switching >> benchmarks. >> >> The patch you did (and along with that some older SMTC changes by Kevin) >> can be done slightly more elegant because we already have: >> >> #define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK) >> >> in <asm/mmu_context.h>. >> >> We used to optimize the ASID managment code by code patching even, see >> mmu_context.h in 78c388aed2b7184182c08428db1de6c872d815f5. >> >> Ralf >> >> Signed-off-by: Ralf Baechle <ralf@xxxxxxxxxxxxxx> >> > > This is nice, but you never committed it. Waiting for people to test it - thanks! Committing it now. Ralf
