According to the MIPS64 Privileged Resource Architecture manual, only values of zero may be written to bits 8..10 of CP0 entryhi. We need to add masking by ASID_MASK. Signed-off-by: David Daney <ddaney@xxxxxxxxxxxxxxxxxx> --- arch/mips/include/asm/mmu_context.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h index d7f3eb0..3899f99 100644 --- a/arch/mips/include/asm/mmu_context.h +++ b/arch/mips/include/asm/mmu_context.h @@ -169,7 +169,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, ehb(); /* Make sure it propagates to TCStatus */ evpe(mtflags); #else - write_c0_entryhi(cpu_context(cpu, next)); + write_c0_entryhi(cpu_context(cpu, next) & ASID_MASK); #endif /* CONFIG_MIPS_MT_SMTC */ TLBMISS_HANDLER_SETUP_PGD(next->pgd); @@ -229,7 +229,7 @@ activate_mm(struct mm_struct *prev, struct mm_struct *next) ehb(); /* Make sure it propagates to TCStatus */ evpe(mtflags); #else - write_c0_entryhi(cpu_context(cpu, next)); + write_c0_entryhi(cpu_context(cpu, next) & ASID_MASK); #endif /* CONFIG_MIPS_MT_SMTC */ TLBMISS_HANDLER_SETUP_PGD(next->pgd); -- 1.6.0.6
