linux kernel wrote:
Hi, This might seem as an unusal feasibility question, but I would like to discuss this here at LKML to hear you views on this matter. The idea would be to build a IBM cell blade lookalike architecture, using full blown linux on core 0, using the other cores as worker threads. Possible target CPUs are Octeon II with 32 cores or more. The main goal for this would be to reduce interrupt latency for worker cores, having them run possibly bare-bone with an IPC method between core 0 and worker cores. probably DMA and HW IRQs.
As you may be aware, this is a common use case for current users of Octeon SOCs.
Is there an existing system design in the kernel already that I can expand/use ? Perhaps expanding/porting the cell blade IPC method. What would you guys think would be the most efficient approach(and perhaps would be acceptable to the LK maintainers for merging at a later stage :) ) ?
Current Octeon applications, architected as you indicate, typically use the SOC's work queue hardware for IPC, but this is via custom drivers, not any existing kernel framework.
Since one of my main job functions is kernel development for the Octeon family, I would certainly be interested in any work done in this area.
David Daney
