On Tue, 19 May 2009, linux kernel wrote: > This might seem as an unusal feasibility question, but I would like to > discuss this here at LKML to hear you views on this matter. > The idea would be to build a IBM cell blade lookalike architecture, > using full blown linux on core 0, using the other cores as worker > threads. > Possible target CPUs are Octeon II with 32 cores or more. > > The main goal for this would be to reduce interrupt latency for worker > cores, having them run possibly bare-bone with an IPC method between > core 0 and worker cores. probably DMA and HW IRQs. > > Is there an existing system design in the kernel already that I can > expand/use ? Perhaps expanding/porting the cell blade IPC method. > What would you guys think would be the most efficient approach(and > perhaps would be acceptable to the LK maintainers for merging at a > later stage :) ) ? I'm not sure if there is a ready to use implementation available anywhere, but what you've described is one of the proposed use models for the MIPS 34K core. Of course the method of communication would differ. You may want to search the Internet to see if you can find anything relevant. Since the Octeon is a MIPS architecture implementation too I've cc-ed the linux-mips list, where you might be able to get additional responses; also about the 34K. Maciej
