Maciej W. Rozycki wrote:
On Thu, 23 Oct 2008, ddaney@xxxxxxxxxxxxxxxxxx wrote:
From: David Daney <ddaney@xxxxxxxxxxxxxxxxxx>
On Cavium, the ebase isn't just CAC_BASE, but also the part of
read_c0_ebase() too.
How is that unique to CONFIG_CPU_CAVIUM_OCTEON? That's a general feature
of the MIPS revision 2 architecture, so please make it right from the
beginning. You'll avoid an ugly #ifdef this way too.
Thanks for the feedback. We will submit a patch that uses the runtime
value of mipsr2 to do the adjustment.
David Daney
