If a cpu is WEAK_ORDERING schouldn't it do a sync independent of CONFIG_SMP ? And if it is a SMP system schouldn't it do a sync independent of CONFIG_WEAK_ORDERING ? And if a cpu has no sync with LLSC schouldn't it do a sync independent of CONFIG_SMP ? All together, is the following the right thing to do ? --- arch/mips/include/asm/barrier.h | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h index 8e9ac31..46b2364 100644 --- a/arch/mips/include/asm/barrier.h +++ b/arch/mips/include/asm/barrier.h @@ -130,12 +130,13 @@ #endif /* !CONFIG_CPU_HAS_WB */ -#if defined(CONFIG_WEAK_ORDERING) && defined(CONFIG_SMP) +#if defined(CONFIG_WEAK_ORDERING) || defined(CONFIG_SMP) #define __WEAK_ORDERING_MB " sync \n" #else #define __WEAK_ORDERING_MB " \n" #endif -#if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP) + +#if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) #define __WEAK_LLSC_MB " sync \n" #else #define __WEAK_LLSC_MB " \n" -- 1.6.0.2
