On Sun, 28 Sep 2008 07:09:35 +0900, Tejun Heo <htejun@xxxxxxxxx> wrote: > >>>> Do you mean __ide_flush_dcache_range? This is needed to avoid cache > >>>> inconsistency on PIO drive. PIO transfer only writes to cache but > >>>> upper layers expects the data is in main memory. > >>> Hum, then I wonder why it's MIPS specific... > >> SPARC also have it. And there were some discussions for ARM IIRC. > > > > I was under the impression that it has been addressed by Tejun at > > the higher-layer level (for both ide/libata) long time ago and that > > MIPS/SPARC code are just a left-overs which could be removed now? > > cc'ing Jens and James. IIRC, I posted several patches but they never > went in. I don't remember what the objections were or whether any > alternative fix went in. I suppose you mean thread http://lkml.org/lkml/2006/1/13/156. IIUC flushing in ide string ops is still needed for MIPS. --- Atsushi Nemoto
