Atsushi Nemoto wrote:
+ /* + * If only one of XFERINT and HOST was asserted, mask + * this interrupt and wait for an another one. Note
This comment somewhat contradicts the code which returns 1 if only HOST interupt is asserted if ERR is set.
Which is not its business to test. I think you should remove that above check -- if there's INTRQ asserted, then it's asserted. I wonder if BMIDE interrupt bit gets set in that case (suspecting it's not)...
Well, let me explain a bit. The datasheed say I should wait _both_ XFERINT and HOST interrupt. So, if only one of them was asserted, I mask it and wait another one. But on the error case, only HOST was asserted and XFERINT was never asserted. Then I could not exit from "waiting another one" state, until timeout.
Hmm, I got it: you decide whether it's worth waiting more for XFEREND interrupt based on whether ERR is set or not. I suppose IDE_INT doesn't get set in case the command gets endede with ERR set?
MBR, Sergei
