Re: [PATCH 1/1] mips: clear IV bit in CP0 cause if the CPU doesn't support divec

[tsbogend@xxxxxxxxxxxxxxxx (Thomas Bogendoerfer)]

On Tue, Sep 09, 2008 at 10:15:25AM +0200, Thomas Petazzoni wrote:
> +	else {
> +		clear_c0_cause(CAUSEF_IV);
> +	}

so we now touch a bit, which is at least marked reserved for R10k CPUs
and hope nobody did something else with it ?

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessary a
good idea.                                                [ RFC1925, 2.3 ]