David Daney wrote: > Esteemed kernel hackers, > > To follow is my third pass at MIPS watch register support. > I think there will have to be at least one more pass at this. The current design assumes that all debug registers support an identical set of the I, R, and W bits and Mask. However sections 8.23 and 8.24 of my MIPS32® Architecture For Programmers Volume III: The MIPS32® Privileged Resource Architecture indicate that they do not have to uniform. I will have to augment the ptrace structures to report the values for each register instead of a single global value. David Daney
