[PATCH v2 1/2] OCTEON: Add processor-specific constants and detection of CPU variants

[Tomaso Paoletti <tpaoletti@xxxxxxxxxxxxxxxxxx>]

Add:
- Processor ID constants specific to Cavium;
- MODULE_PROC_FAMILY string for OCTEON;
- Probe function to detect all processor variants;
- Proper cpu_to_name() case.

Signed-off-by: Tomaso Paoletti <tpaoletti@xxxxxxxxxxxxxxxxxx>
---
 arch/mips/kernel/cpu-probe.c |   35 +++++++++++++++++++++++++++++++++++
 include/asm-mips/cpu.h       |   14 ++++++++++++++
 include/asm-mips/module.h    |    2 ++
 3 files changed, 51 insertions(+), 0 deletions(-)

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 335a6ae..3e104db 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -160,6 +160,7 @@ static inline void check_wait(void)
 	case CPU_25KF:
 	case CPU_PR4450:
 	case CPU_BCM3302:
+	case CPU_CAVIUM_OCTEON:
 		cpu_wait = r4k_wait;
 		break;
 
@@ -821,6 +822,35 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
 	}
 }
 
+static inline void cpu_probe_cavium(struct cpuinfo_mips *c)
+{
+	switch (c->processor_id & 0xff00) {
+	case PRID_IMP_CAVIUM_CN38XX:
+	case PRID_IMP_CAVIUM_CN31XX:
+	case PRID_IMP_CAVIUM_CN30XX:
+	case PRID_IMP_CAVIUM_CN58XX:
+	case PRID_IMP_CAVIUM_CN56XX:
+	case PRID_IMP_CAVIUM_CN50XX:
+	case PRID_IMP_CAVIUM_CN52XX:
+		c->cputype = CPU_CAVIUM_OCTEON;
+		break;
+	default:
+		printk(KERN_INFO "Unknown Octeon chip!\n");
+		c->cputype = CPU_UNKNOWN;
+		break;
+	}
+
+	c->isa_level = MIPS_CPU_ISA_M64R2;
+	c->options = MIPS_CPU_TLB |     /* CPU has TLB */
+		     MIPS_CPU_4KEX |    /* "R4K" exception model */
+		     MIPS_CPU_COUNTER | /* Cycle count/compare */
+		     MIPS_CPU_WATCH |   /* watchpoint registers */
+		     MIPS_CPU_DIVEC |   /* dedicated int vector */
+		     MIPS_CPU_EJTAG |   /* EJTAG exception */
+		     MIPS_CPU_LLSC;     /* CPU has ll/sc instructions */
+	decode_config1(c);
+}
+
 const char *__cpu_name[NR_CPUS];
 
 /*
@@ -902,6 +932,8 @@ static __cpuinit const char *cpu_to_name(struct cpuinfo_mips *c)
 	case CPU_BCM4710:	name = "Broadcom BCM4710"; break;
 	case CPU_PR4450:	name = "Philips PR4450"; break;
 	case CPU_LOONGSON2:	name = "ICT Loongson-2"; break;
+	case CPU_CAVIUM_OCTEON:	name = "Cavium Octeon"; break;
+
 	default:
 		BUG();
 	}
@@ -941,6 +973,9 @@ __cpuinit void cpu_probe(void)
 	case PRID_COMP_NXP:
 		cpu_probe_nxp(c);
 		break;
+	case PRID_COMP_CAVIUM:
+		cpu_probe_cavium(c);
+		break;
 	default:
 		c->cputype = CPU_UNKNOWN;
 	}
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index 229a786..c018727 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -33,6 +33,7 @@
 #define PRID_COMP_TOSHIBA	0x070000
 #define PRID_COMP_LSI		0x080000
 #define PRID_COMP_LEXRA		0x0b0000
+#define PRID_COMP_CAVIUM	0x0d0000
 
 
 /*
@@ -114,6 +115,18 @@
 #define PRID_IMP_BCM3302	0x9000
 
 /*
+ * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM
+ */
+
+#define PRID_IMP_CAVIUM_CN38XX 0x0000
+#define PRID_IMP_CAVIUM_CN31XX 0x0100
+#define PRID_IMP_CAVIUM_CN30XX 0x0200
+#define PRID_IMP_CAVIUM_CN58XX 0x0300
+#define PRID_IMP_CAVIUM_CN56XX 0x0400
+#define PRID_IMP_CAVIUM_CN50XX 0x0600
+#define PRID_IMP_CAVIUM_CN52XX 0x0700
+
+/*
  * Definitions for 7:0 on legacy processors
  */
 
@@ -203,6 +216,7 @@ enum cpu_type_enum {
 	 * MIPS64 class processors
 	 */
 	CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
+	CPU_CAVIUM_OCTEON,
 
 	CPU_LAST
 };
diff --git a/include/asm-mips/module.h b/include/asm-mips/module.h
index de6d09e..7b24183 100644
--- a/include/asm-mips/module.h
+++ b/include/asm-mips/module.h
@@ -114,6 +114,8 @@ search_module_dbetables(unsigned long addr)
 #define MODULE_PROC_FAMILY "SB1 "
 #elif defined CONFIG_CPU_LOONGSON2
 #define MODULE_PROC_FAMILY "LOONGSON2 "
+#elif defined CONFIG_CPU_CAVIUM_OCTEON
+#define MODULE_PROC_FAMILY "OCTEON "
 #else
 #error MODULE_PROC_FAMILY undefined for your processor configuration
 #endif
-- 
1.5.3.2