On Thu, Aug 21, 2008 at 06:03:43PM +0200, Takashi Iwai wrote:
> > Thanks for clarification.
> > How about the revised patch below (for PARISC)?
the PARISC part will not work for 735 systems, because the CPU can't
map memory uncached, iirc.
> ... and the below is for MIPS.
for most MIPS system you need the same trick as for PARISC and use
uncached memory. But there are systems, which can't use uncached
memory.
One of the is SGI IP28, which needs to be switched to a special
slower mode for uncached accesses, which we avoid completly in the
kernel right now and I don't think making the switch to slow mode
possible in user space is a good idea.
SGI Origin 200/2000, SGI Onyx and some Challenge Systems have a
different problem:
"Uncached Memory Access in SGI Origin 2000 and in Challenge and Onyx Series
Access to uncached memory is not supported in these systems, in which
cache coherency is maintained by the hardware, even under access from
CPUs and concurrent DMA. There is never a need (and no approved way)
to access uncached memory in these systems."
That's from the IRIX Device Driver guide.
Right now I can't think of a solutin, which works on every MIPS system.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessary a
good idea. [ RFC1925, 2.3 ]
