I am having a similar problem where complicated bash scripts on boot randomly
throw SIGILL. I am running on a PMC MSP8510 platform - E9000 core. I have
applied the patch to "war.h" mentioned in this thread and that did greatly
reduce the number of occurences of this problem but has not fixed it. I was
getting at least 2 illegal instructions every boot and now I can boot
without any problems about 90% of the time.
Does the patch you mention below apply to the E9000 core as well?
Ralf Baechle DL5RB wrote:
>
> Signed-off-by: Ralf Baechle <ralf@xxxxxxxxxxxxxx>
>
> diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
> index f599e79..7ee0cb0 100644
> --- a/arch/mips/kernel/cpu-probe.c
> +++ b/arch/mips/kernel/cpu-probe.c
> @@ -75,6 +75,26 @@ static void r4k_wait_irqoff(void)
> local_irq_enable();
> }
>
> +/*
> + * The RM7000 variant has to handle erratum 38. The workaround is to not
> + * have any pending stores when the WAIT instruction is executed.
> + */
> +static void rm7k_wait_irqoff(void)
> +{
> + local_irq_disable();
> + if (!need_resched())
> + __asm__(
> + " .set push \n"
> + " .set mips3 \n"
> + " .set noat \n"
> + " mfc0 $1, $12 \n"
> + " sync \n"
> + " mtc0 $1, $12 \n"
> + " wait \n"
> + " .set pop \n");
> + local_irq_enable();
> +}
> +
> /* The Au1xxx wait is available only if using 32khz counter or
> * external timer source, but specifically not CP0 Counter. */
> int allow_au1k_wait;
> @@ -132,7 +152,6 @@ static inline void check_wait(void)
> case CPU_R4700:
> case CPU_R5000:
> case CPU_NEVADA:
> - case CPU_RM7000:
> case CPU_4KC:
> case CPU_4KEC:
> case CPU_4KSC:
> @@ -142,6 +161,10 @@ static inline void check_wait(void)
> cpu_wait = r4k_wait;
> break;
>
> + case CPU_RM7000:
> + cpu_wait = rm7k_wait_irqoff;
> + break;
> +
> case CPU_24K:
> case CPU_34K:
> cpu_wait = r4k_wait;
>
>
>
--
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